Semiconductor memory device and method for masking...

Details Semiconductor memory device and method for masking... Semiconductor memory device and method for masking...

2006-08-29

2006-08-29

Tran, Michael T. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S193000

Reexamination Certificate

active

07099207

ABSTRACT:
A semiconductor device includes a memory cell array, including at least one of a plurality of memory cells storing program data received from a flash memory, a row address buffer, which receives a row address signal in response to a first strobe signal, and a column address buffer, which receives a column address signal in response to a second strobe signal. The device further includes a write protection circuit, enabled/disabled in response to a first control signal, the write protection circuit outputting a masking control signal in response to the row address signal, the second strobe signal, and second control signals when enabled, and a column decoder, which decodes the column address signal in response to the masking control signal and enables at least one of a plurality of column selection lines of the memory cell array, corresponding to the decoded column address signal, or disables the column selection lines.

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English Abstract***.

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