Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-07-26
2003-07-29
Hu, Shouxiang (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S305000
Reexamination Certificate
active
06600187
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method for manufacturing the same, and more particularly, to a semiconductor memory device in which the characteristics of a plurality of unit elements having different geometrical structures, for example, transistors, are not deteriorated.
2. Description of the Related Art
As the integration density of semiconductor memory devices increases, the sizes of unit elements becomes smaller. In particular, as the size of a cell transistor is reduced, a short channel phenomenon occurs, in which a threshold voltage is reduced and leakage current increases. Accordingly, the dynamic refresh characteristics of a dynamic random access memory (DRAM) are deteriorated. In order to solve such problems, the concentration of impurities of a substrate is increased by implanting P-type (or N-type) impurity ions into the substrate before forming a gate electrode in an N-channel transistor (or a P-channel transistor) for increasing the threshold voltage.
Also, in order to form N-type (P-type) source and drain regions in the case of an N-channel transistor (or a P-channel transistor), the concentration of the impurities of the source and drain regions must be greater than the concentration of the channel region. As the size of the transistor is reduced, the concentration of impurities implanted by ion implantation for suppressing change in the threshold voltage must increase. Therefore, the difference between the concentration of the impurities of the source and drain regions of the transistor and the concentration of the impurities of the channel region is reduced as the integration density increases. Therefore, the resistance in a contact surface between the source and drain regions and the channel region increases. Accordingly, the operation speed of the transistor is reduced.
Furthermore, since the concentration of impurity ions for controlling the threshold voltage of the substrate (or a well formed in the substrate) increases as the integration density increases, leakage current that can flow from the source and drain regions to the substrate (or the well) increases. In order to solve such problems, an ion implantation technology by which an impurity region is partially formed only under the channel region of the transistor and not in the entire substrate in which the transistor is to be formed, using a reverse gate pattern, is disclosed in the U.S. Pat. No. 5,904,530 and Japanese Journal of Applied Physics; 1998, 1059.
It is most preferable to simultaneously form the transistors of the cell region of a semiconductor memory device and the transistors of a core circuit/peripheral circuit regions using the method disclosed in the above-mentioned publications in order to simplify manufacturing processes. Since all the transistors of the cell region constitute a part of a memory device, the lengths of all gates are equal. However, the transistors of the core circuit/peripheral circuit regions are designed to have different lengths depending on the purposes of the respective transistors, in which some transistors are used to constitute differential amplifiers and other transistors are used to constitute drivers. At this time, even though the thickness of a conductive material deposited for forming a gate is the same in the cell region and the core circuit/peripheral circuit regions, since it is determined whether or not to fill a trench depending on the width of the trench provided in an insulating layer or the thickness of the deposited material, the height of the gate differs in each region in a successive etch back process. It is possible to perform the etch back process in the core circuit/peripheral circuit regions separately from the etch back process in the cell region, in order to manufacture the gates of the core circuit/peripheral circuit regions as designed. Since the lengths of the gates of the transistors of the core circuit/peripheral circuit regions vary, although an etch back time is controlled in order to manufacture some gates as designed, the other gates are not manufactured as desired. It is possible to obtain the gates of the cell region and the core circuit/peripheral circuit regions as designed by performing etch back processes corresponding to the respective lengths of the gates of the core circuit/peripheral circuit regions. However, in this case, processes become complicated.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having elements whose geometrical structures are different from each other, in which it is possible to maintain the characteristics of elements, for example, transistors formed in some regions, whose geometrical structures are different from other elements formed in other regions without deterioration of the characteristics of the other elements in other regions, and a method for manufacturing the same.
Accordingly, to achieve the above object, according to an aspect of the present invention, there is provided a first transistor comprised of a first gate, a first gate insulating film, a first source region, and a first drain region formed in a semiconductor substrate in core circuit/peripheral circuit regions of a semiconductor memory device having a cell region comprised of elements having a uniform standard, for example, a transistor (a second transistor) and the core circuit/peripheral circuit regions comprised of elements having various standards, for example, a transistor (a first transistor), a planarized interlayer dielectric film which covers the first transistor, and a second transistor formed in the cell region, comprising a second source region, a second drain region, a second gate having a height corresponding to the height of the interlayer dielectric film, and a second gate insulating film.
The second gate can be formed to be level with the interlayer dielectric film. When the height of the interlayer dielectric film increases, the height of the second gate also increases.
The first transistor further comprises a first spacer formed on the side wall of the first gate, the second gate of the second transistor is in the form of a concave lens, and the second transistor further comprises a second spacer formed on the side wall of the second gate. The second spacer is a first insulating film formed of a material having a high etch selectivity with respect to the interlayer dielectric film under a predetermined etchant. The interlayer dielectric film is a silicon nitride film, a silicon oxide film, a phosphosilicate glass (PSG) film, a borosilicate glass (BSG) film, a borophosphosilicate glass (BPSG) film, a tetraethylorthosilicate glass (TEOS) film, an ozone-TEOS film, an undopedsilicate glass (USG) film, or a combination of the above films and the first insulating film is the silicon nitride film, an aluminum oxide film, or a tantalum oxide film.
The second gate is formed of a polysilicon layer and a refractory metal layer and further comprises a second insulating film formed of a material having high etch selectivity with respect to the interlayer dielectric film formed on the refractory metal layer under a predetermined etchant. The second gate is formed of a polysilicon layer and a refractory metal layer and further comprises a second insulating film formed of a material having high etch selectivity with respect to the interlayer dielectric film formed on the refractory metal layer under a predetermined etchant.
The refractory metal layer is Co, W, Ta, Mo, or Ti. The refractory metal silicide layer is CoSi
x
, TiSi
x
, TaSi
x
, MoSi
x
, WSi
x
, or PtSi
x
. The second insulating film is the silicon nitride film, an aluminum oxide film, or a tantalum oxide film.
The first transistor further comprises a third insulating film formed on the top of the first gate and the second insulating film is thicker than the third insulating film. The thickness of the third insulating film is between 1500 and 2500 (Å).
In order to protect the semiconductor substrate and th
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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