Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-09-19
2004-04-27
Nguyen, Cuong (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S309000
Reexamination Certificate
active
06727542
ABSTRACT:
CROSS REFERENCES TO RELATED APPLICATIONS
This application claims priority under 35 U.S.C. §119 from Korean Patent Application No. 2002-2509, filed on Jan. 16, 2002, the entirety of which is hereby incorporated by reference as if fully set forth herein.
BACKGROUND
1. Field of the Invention
The present invention relates to a semiconductor memory device and method for manufacturing the same, and more particularly, to a dynamic random access memory (DRAM) having a stack-shaped capacitor and a method for manufacturing the same.
2. Description of the Related Art
A dynamic random access memory (DRAM) among semiconductor memory devices is comprised of one transistor and one capacitor. Thus, in order to serve as a memory device, the DRAM must have sufficient capacitance. There is no problem when the design rule of the memory device is wide. However, as the memory device becomes highly integrated, its design rule becomes extremely dense and an area for each memory device becomes narrower, and thus, area per cell also decreases. A stack-shaped capacitor has been developed to obtain sufficient capacitance as the area becomes narrower. The stack-shaped capacitor can increase a surface area by forming an electrode with high depth even though the occupied area of the capacitor decreases. Thus the required capacitance of the capacitor can be obtained even though the design rule of the memory device becomes finer. However, in the stack-shaped capacitor, when the stack-shaped capacitor forms a storage node, a step between the cell area and a peripheral area becomes very severe. As a result, a metal interconnection process cannot be performed well due to an extreme pattern-thinning phenomenon caused by diffraction and irregular reflection of light, which is exposed due to a high step between a cell area and the peripheral area during a subsequent photolithographic process for metal interconnections in a case where a predetermined planarization process is not performed.
Thus, in a conventional planarization process between the cell area and the peripheral area, a very thick interlayer dielectric (ILD) film is formed on the surface of a semiconductor substrate after a capacitor process is completed. The cell area having a high step is opened after a predetermined photolithographic process, and then, the ILD film in the cell area is etched to a predetermined thickness through dry etching, and thereby removed. Then, the step between the cell area and the peripheral area is slightly decreased. The thick ILD film is again formed on the surface of the semiconductor substrate and is polished and removed and thereby planarized to enable the metal interconnection process on the entire surface of the semiconductor substrate through chemical mechanical polishing (CMP).
However, the photolithographic process for opening the cell area and a dry etching process is added to the conventional planarization process between the cell area and the peripheral area, and an additional planarization process using CMP is accompanied by a subsequent process, thus increasing the number of processes. Moreover, the photolithographic process and the CMP process are included, and thus the reliability of production is reduced, and the period of a manufacturing process becomes longer, and costs increase.
SUMMARY
To solve the above problems, it is an object of the present invention to provide a semiconductor memory device and a method for manufacturing the same in which manufacturing processes are simplified, and a wide contact area is formed on a plate electrode for serving as the ground electrode of a capacitor so that a step between a cell area of a semiconductor chip and a peripheral area formed by a capacitor formed in the cell area is effectively decreased, thereby greatly reducing ground resistance, thus improving the electric characteristics of a memory device.
Accordingly, to achieve the above object, according to one embodiment, there is provided a semiconductor memory device. The semiconductor memory device includes an oxide layer for isolating individual devices which define device areas so that a cell area and a peripheral circuit area are separated from each other on a semiconductor substrate. The semiconductor memory device also includes: a plurality of MOS transistors, which are comprised of source areas, drain areas, and gates that are formed in the cell area and the peripheral circuit area; a bit line, which is formed on the plurality of MOS transistors and is electrically connected to the MOS transistors; a stack-shaped capacitor, which is comprised of a first electrode, a dielectric layer, and a second electrode between which the MOS transistors and the bit line in the cell area are interposed; a guard-ring pattern, which is interposed between the cell area and the peripheral circuit area; surrounds the cell area and is apart from the peripheral circuit area, and a contact fill for a plate electrode, which is formed in the guard-ring pattern and is in contact with the second electrode that is formed on the internal sidewall and the bottom of the guard-ring pattern.
The first electrode of the stack-shaped capacitor is electrically connected to the source areas and has a hollow cylindrical shape so that the area of a capacitor per area is increased, and capacitance is maximized. The first electrode is conductive polycrystalline silicon (polysilicon) such as an impurity-doped polycrystalline silicon, and further includes a barrier layer such as platinum (Pt), RuO, Rb, and RbO. The dielectric layer may be a combination layer of a silicon oxide layer and a silicon nitride layer, but is preferably formed of a high dielectric material that is at least one selected from Ta
2
O
5
, PZT, PZLT, BST, and Al
2
O
3
, such that the capacitance of the capacitor is increased for a given area.
The second electrode is formed in a block form to overlap a predetermined region adjacent to the peripheral circuit area including the entire cell area, and the second electrode is conductive polysilicon, such as an impurity-doped polysilicon, and the second electrode further includes a barrier layer, thereby preventing impurity atoms constituting a high dielectric layer from penetrating into junctions that are formed on a lower portion of the semiconductor memory device and thereby deteriorating electrical characteristics.
The guard-ring pattern is formed on the same surface as the bottom of the first electrode, and the second electrode is extended to the edge of the cell area on the bottom of the guard-ring pattern. At least a part of the contact fill for the plate electrode is electrically connected to the second electrode in the guard-ring pattern. The contact fill for the plate electrode includes a tungsten fill that is formed of tungsten in the center, and barrier metal that is formed outside of the tungsten fill adjacent to a recessed portion, thereby preventing the formation of fluoric components that penetrate into a lower MOS transistor from a tungsten (W) layer, which is a filling metal layer. The barrier metal is a combination layer of Ti and TiN.
To achieve the above object, according to another embodiment, there is provided a method for manufacturing a semiconductor memory device. A cell area is separated from a peripheral circuit area on a semiconductor substrate to form device active areas. A plurality of MOS transistors are formed in the device active areas of the cell area and the peripheral circuit area. A first interlayer dielectric (ILD) film is formed on the semiconductor substrate and a first electrode pattern and a guard-ring pattern surrounding the cell area are formed on the first ILD film. A conductive layer for a first electrode and an insulating layer for patterning are sequentially formed on the first electrode pattern and the guard-ring pattern. The entire cell area and a part of the guard-ring pattern are opened, and the conductive layer for the first electrode and the insulating layer for patterning are removed to the first ILD film, and a first electrode node in the cell area is formed. The insulating lay
Kim Ki-Nam
Park Byung-Jun
Nguyen Cuong
Samsung Electronics Co,. Ltd.
Volentine & Francos, PLLC
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