Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-05-05
2000-10-24
Smith, Matthew
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438 3, 438644, H01L 218242
Patent
active
061366390
ABSTRACT:
A semiconductor memory device and method of fabricating the same, which improves adhesion of the lower electrode of a ferroelectric planar capacitor, and prevents inter-diffusion between the Pt electrode of the capacitor and adhesion layer placed under the Pt electrode. The semiconductor memory device includes an insulating layer formed on a substrate, a paraelectric layer formed on the insulating layer, and a conductive layer formed on the paraelectric layer.
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K. Sreenivas et al., "Investigation of Pt/Ti Bilayer Metallization on Silicon for Ferroelectric Thin Film Integration", J. Appl. Phys., vol. 75, No. 1, Jan. 1994, pp. 232-239.
Lee Calvin
LG Semicon Co. Ltd.
Smith Matthew
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