Semiconductor memory device and method for controlling its outpu

Details Semiconductor memory device and method for controlling its outpu Semiconductor memory device and method for controlling its outpu

1992-09-24

1994-05-03

LaRoche, Eugene R.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365220, 365233, G11C 700

Patent

active

053093984

ABSTRACT:
An upper column address strobe signal and a lower column address strobe signal applied to a dynamic RAM are 180.degree. out of phase from each other. Data of n bits are read out from a memory cell array at a time. The data read out from memory cell array is divided into two bit groups and applied to an upper IO buffer and a lower IO buffer. Upper IO buffer and lower IO buffer latch sequentially the upper bit group and the lower bit group and output these groups to a data transmission bus in response to the upper column address strobe signal and the lower column address strobe signal.

REFERENCES:
patent: 4928265 (1990-05-01), Higuchi et al.

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