Semiconductor memory device and method for controlling clock...

Details Semiconductor memory device and method for controlling clock... Semiconductor memory device and method for controlling clock...

2011-08-30

2011-08-30

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

C711S103000, C711SE12001

Reexamination Certificate

active

08010765

ABSTRACT:
In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

REFERENCES:
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patent: 2003/0099243 (2003-05-01), Oh et al.
patent: 2008/0072115 (2008-03-01), Cho et al.
patent: 2002-0014563 (2002-02-01), None
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patent: 2005-0101034 (2005-10-01), None
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Jun Pang et al, “A Priority-Expression-Based Burst Scheduling of Memory Reordering Access”, Embedded Computer Systems: Architectures, Modeling, and Simulation, International Conference on Digital Object Identifier, 2008 , pp. 203-209.
English language abstract of Korean Publication No. 2002-0014563.
English language abstract of Korean Publication No. 10-0422954.
English language abstract of Korean Publication No. 2005-0101034.

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