Semiconductor memory device and method for arranging and...

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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C365S189110, C365S177000, C365S063000

Reexamination Certificate

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07315466

ABSTRACT:
A semiconductor device and method for arranging and manufacturing the same are disclosed. The semiconductor device includes a plurality of inverters including at least one first pull-up transistor and first pull-down transistor and inverting and outputting an input signal, respectively; and a plurality of NAND gates including at least two second pull-up transistor and second pull-down transistor and generating an output signal having a high level if at least one of at least two input signals has a low level, respectively, wherein the at least one first pull-up transistor and first pull-down transistor and the at least two second pull-up transistor and second pull-down transistor are stacked and arranged on at least two layers.

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Jung et al., The Revolutionary and Truly 3-dimensional 25F2SRAM Technology with the smallest S3(Stacked Single-crystal Si) Cell, 0.16 um2, and SSTFT (Stacked Single-crystal Thin Film Transistor) for Ultra High Density SRAM, Symposium on VLSI Technology Digest of Technical Papers, 2004, pp. 228-229.
Partial European Search Report, European Application No. 05 01 6656, Apr. 13, 2007.

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