Semiconductor memory device and latency signal generating...

Details Semiconductor memory device and latency signal generating... Semiconductor memory device and latency signal generating...

2006-05-03

2008-11-18

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000

Reexamination Certificate

active

07453745

ABSTRACT:
A latency signal generating method and a corresponding semiconductor memory device, among other things, are disclosed. Such a method includes: receiving a clock signal for the semiconductor memory device; receiving a mode characterization signal; providing the DQS; and adapting the duration of a preamble state of the DQS according to the mode characterization signal to promote conformance of a strobe state of the DQS with the clock signal.

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Korean Notice of Allowability dated Jul. 27, 2007.
JEDEC Standard “Double Data Rate (DDR) SDRAM Specification,” JESD79D, Jan. 2004.

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