Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2008-09-29
2010-10-26
Le, Vu A (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S189120
Reexamination Certificate
active
07821846
ABSTRACT:
A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.
REFERENCES:
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 5973988 (1999-10-01), Nakahira et al.
patent: 6693832 (2004-02-01), Ok
patent: 7102958 (2006-09-01), Lee et al.
patent: 7304906 (2007-12-01), Ha et al.
patent: 2007/0088921 (2007-04-01), Kim et al.
patent: 2007/0147148 (2007-06-01), An
patent: 2007/0180202 (2007-08-01), Kawabata et al.
patent: 2008/0002804 (2008-01-01), Jeong
patent: 2000-030464 (2000-01-01), None
patent: 2005-322251 (2005-11-01), None
patent: 1020040034168 (2004-04-01), None
Notice of Allowance issued from Korean Intellectual Property Office on Jan. 28, 2010.
Hynix / Semiconductor Inc.
IP & T Law Firm PLC
Le Vu A
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