Semiconductor memory device and its driving method

Details Semiconductor memory device and its driving method Semiconductor memory device and its driving method

2008-09-29

2010-10-26

Le, Vu A (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189120

Reexamination Certificate

active

07821846

ABSTRACT:
A semiconductor memory device including a first latch that latches a Mode Register Set (MRS) code consisting of multiple bits in response to an MRS command pulse, a code controller that generates a control signal in response to a code value of preset bits out of an output signal from the first latch, a second latch that selectively latches the output signal from the first latch in response to the control signal and a mode decoder that decodes an output signal from the second latch to output an operation mode.

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Notice of Allowance issued from Korean Intellectual Property Office on Jan. 28, 2010.

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