Semiconductor memory device and data error detection and...

Details Semiconductor memory device and data error detection and... Semiconductor memory device and data error detection and...

2011-05-24

2011-05-24

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S801000, C714S042000, C714S718000, C714S719000, C714S758000, C365S185090

Reexamination Certificate

active

07949928

ABSTRACT:
A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.

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