Semiconductor memory device and current mirror circuit

Details Semiconductor memory device and current mirror circuit Semiconductor memory device and current mirror circuit

2006-02-14

2006-02-14

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189070, C365S189090, C365S210130, C365S226000

Reexamination Certificate

active

06999365

ABSTRACT:
A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

REFERENCES:
patent: 6233189 (2001-05-01), Tanzawa et al.
patent: 6504778 (2003-01-01), Uekubo
patent: 6567330 (2003-05-01), Fujita et al.
patent: 6788601 (2004-09-01), Takano et al.
patent: 2000-353394 (2000-12-01), None
Shigeru Atsumi et al., “A Channel-Erasing 1.8-V-Only 32-Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme”, IEEE Journal of Solid-State Circuits, vol. 35, No. 11, Nov. 2000. pp 1648-1653.
Shigeru Atsumi et al., “A Channel-Erasing 1.8V-Only 32Mb NOR Flash EEPROM with a Bitline Direct Sensing Scheme”, ISSCC 2000, Session 16, Non-Volatile and SRAM, Paper TP 16.7, Digest of Technical Papers, pp 276-277.

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