Semiconductor memory device and current mirror circuit

Details Semiconductor memory device and current mirror circuit Semiconductor memory device and current mirror circuit

2002-11-26

2004-09-07

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S189070, C365S189090, C365S210130, C365S226000

Reexamination Certificate

active

06788601

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATION
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-370504, filed on Dec. 4, 2001; the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device that stores data in accordance with the presence/absence or the magnitude of a current. More particularly it relates to an improvement in a sense amp circuitry operative to compare a potential on a data line with that on a reference data line for data sensing.
2. Description of the Related Art
An EEPROM is known as an electrically rewritable semiconductor memory device for nonvolatile storage of data. A type of EEPROM can erase multiple memory cells collectively at a time, which is called the flash memory. Such the semiconductor memory stores data in a memory cell in accordance with the presence/absence or the magnitude of a current flowing in it and accordingly employs a sense amp circuit of a current read-out type. A type of such the sense amp often employed compares a voltage caused on a data line based on data read out of a memory cell with a reference voltage on a reference voltage line for data determination.
FIG. 19
shows an arrangement of such the sense amp circuit in the art. A sense amp body
311
comprises a differential amp (opamp) OP. The differential amp OP has two input terminals connected to a sense line SN and a reference sense line RSN, respectively. The sense line SN is connected through a NMOS transistor QN
1
, or an isolator (clamper), to a data line DL that is led to a bit line BL from a selected memory cell MC. The isolator is located to suppress the drain voltage on the memory cell MC below a certain level. A PMOS transistor QP
1
, or a current source load, is also connected to the sense line SN. The PMOS transistor QP
1
and the isolator NMOS transistor QN
1
together configure a cascade amp
310
.
To the reference sense line RSN, a reference voltage generator
320
is connected to generate a middle reference voltage between voltages appeared on the sense line SN based on data. The reference voltage generator
320
comprises a reference cell RMC having the same structure as that of the memory cell MC. It also comprises a current source NMOS transistor QN
11
, which reflects the current flowing through the reference cell RMC to flow a current that is half the current, Icell, flowing through an ON-cell (a cell in a state of data “1”). The current source NMOS transistor QN
11
has a drain connected to the reference sense line RSN via the isolator transistor QN
2
, similar to the sense line SN. A current source load PMOS transistor QP
2
is connected to the reference sense line RSN. The data line DL has a relatively large capacitance in general. Therefore, a dummy capacitor CR is connected to a reference data line RDL to match its capacitance with that of the data line DL.
The current path through the reference cell RMC configures a reference cell unit
320
a
, which includes the isolator NMOS transistor QN
4
and the current source load PMOS transistor QP
4
serially connected with the reference cell RMC. In order to transfer the reference current, I
0
, flowing through the reference cell RMC to the current source transistor QN
11
, the current path through the reference transistor QN
10
configures a reference transistor unit
320
b
. It includes the isolator NMOS transistor QN
3
and the current source load PMOS transistor QP
3
serially connected with the current source transistor QN
11
. The current source PMOS transistor QP
3
has a drain node N
1
connected to a gate of the reference NMOS transistor QN
10
.
The PMOS transistors QP
3
and QP
4
configure a current mirror circuit. Accordingly, the current, I
1
, flowing through the reference transistor QN
10
reflects the reference current, I
0
, flowing through the reference cell RMC. In accordance with a size ratio between the PMOS transistors QP
3
and QP
4
, the current I
1
has a constant ratio to the reference current I
0
. The reference NMOS transistor QN
10
and the current source NMOS transistor QN
11
also configure a current mirror circuit. Accordingly, a size ratio between them can be determined so that the current, I
2
, flowing through the current source transistor QN
11
has a constant ratio to I
1
.
This reference voltage generator allows the current source transistor QN
11
to flow a current, Icell/2, where Icell denotes a cell current flowing into a selected memory cell in an ON-cell state. As a result, when the sense amp
311
senses a difference between the voltage on the sense line SN and that on the reference sense line RSN, it is possible to determine whether the data is “1” or “0”.
Such the conventional sense amp circuitry causes a problem associated with a lower supply voltage, which is described below.
FIG. 20
shows voltage distributions in the sense amp circuit when a supply voltage is set to Vcc=2.7V and when Vcc is further lowered. To achieve a cell current necessary for a read operation, a bit line voltage is required to keep a minimum value of 0.5V. A difference in bit line amplitude between an OFF-cell and an ON-cell has an upper limit determined to 0.3V as required for suppressing the so-called soft-write (a little written phenomenon caused by the read operation). A current source load PMOS transistor is assumed to have a threshold value of Vtp=−0.8V. In this case, if Vcc=2.7V, a sense line amplitude is allowed to have a possible range of 1.1V.
Thus, it is possible to hold an operating voltage sufficient to configure the cascade amplifier as shown in
FIG. 19
that includes the isolator interposed between the sense line SN and the data line DL. When lowered to Vcc=1.8V and if the bit line voltage minimum, the bit line amplitude possible range, and the voltage drop corresponding to the threshold value of the current source load PMOS transistor require to keep their voltages unchanged, the sense line amplitude possible range is reduced as shown in FIG.
20
. In this case, it is impossible to hold an amplifying operation from the bit line to the sense line. When lowered to Vcc=1.5V, no operating margin can be held.
In consideration of such the situation, the Inventors et al. have previously proposed a bit-line direct-sensing scheme, as a preferable sense amp circuitry capable of responding to a supply voltage lowered below 2V, in which a sense node is connected directly to a data line without locating an isolator. (See: (1) Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, ICD 200-13; and (2) Atsumi S. et al., “A Channel-Erasing 1.8V-Only 32 Mb NOR Flash EEPROM with a Bit-Line Direct-Sensing Scheme”, ISSCC 2000 Digest of Technical Papers, pp. 276-277 (2000.2)).
Even if the above bit-line direct-sensing scheme is applied, however, the conventional sense amp circuitry has another problem in the reference voltage generator, which prevents the supply voltage to be lowered. This problem is described using the reference voltage generator
320
in FIG.
19
. In order to allow the gate node N
3
of the current source transistor QN
11
to be kept at a constant potential regardless of the power supply Vcc, the reference NMOS transistor QN
10
is required to operate as a pentode. In consideration of this point, a minimum supply voltage, Vccmin, is examined, which allows the reference voltage generator
320
to operate. The isolator NMOS transistors QN
3
and QN
4
are not considered because they can be removed.
When a drain voltage of Vdn=0.8V is required for the reference cell RMC to flow a current through it, and the current source load transistor QP
4
has a threshold voltage of Vtp=−1V, a minimum supply voltage, Vccmin1, at the reference cell unit
320
a
comes to Vccmin1=Vdn+|Vtp|=1.8V.
In contrast, at the reference transistor unit
320
b
, the voltage on the node N
1
requ

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