Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-03-14
2001-12-18
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S203000, C365S208000, C365S205000
Reexamination Certificate
active
06331959
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor storage devices and more particularly to semiconductor storage devices having dynamic sense amplifiers, and methods of controlling such devices.
BACKGROUND OF THE INVENTION
Currently, widely used high-speed memory devices include static random access memories (SRAMs). SRAMs typically include memory cells that place data signals on at least one data line. Such signals are typically a very small variation in potential.
One common way to detect small memory cell data signals is with a dynamic sense amplifier. A dynamic sense amplifier may include a sense amplifier that is controlled according to a dynamic timing signal.
In many arrangements, digit lines may be precharged to high potential relative to the memory device. As but one example, a digit line may be precharged at or very close to a high power supply level (VCC). More particularly, a memory device may precharge two complementary bit lines to a VCC level. Subsequently, a data signal may drive one bit line to a slightly lower level while the other bit line essentially maintains the high level.
A particular example of memory device is shown in
FIGS. 6 and 7
. A memory device can include a precharge and equalize circuit that includes p-channel metal-oxide-semiconductor (PMOS) precharge transistors
600
and
602
and a PMOS equalize transistor
604
. Such a circuit may precharge and equalize complementary bit lines
606
and
608
according to an equalize signal EQ. A word line
610
may connect a memory cell
612
to complementary digit lines (
606
and
608
) and thus place data signals on the complementary digit lines (
606
and
608
). A word line
610
may receive a word line signal Word.
Complementary digit lines (
606
and
608
) can be connected to a sense amplifier
614
by way of a transfer gate circuit that includes PMOS transfer gate transistors
616
and
618
. Transfer gate transistors (
616
and
618
) may be commonly activated by a select signal Yj.
The sense amplifier
614
may include cross-coupled inverter sections
614
-
a
and
614
-
b.
A first sense amplifier input node
614
-
c
can be connected to the output of inverter section
614
-
a
and the input of inverter
614
-
b.
Similarly, a second sense amplifier input node
614
-
d
can be connected to the output of inverter section
614
-
b
and the input of inverter section
614
-
a.
The sense amplifier
614
may be dynamically activated by an n-channel MOS (NMOS) supply transistor
620
. NMOS supply transistor
620
may be activated by a sense enable signal SE
1
.
FIG. 7
shows a timing diagram illustrating a read operation for the circuit of FIG.
6
. Prior to time T
1
, an equalize signal (EQ) is active (low) while a word line signal (Word) is inactive (low).
At time T
1
, the word line signal (Word) is activated while the equalize signal (EQ) is deactivated. Consequently, the precharge and equalization circuit (
600
,
602
and
604
) is disabled while the memory cell
612
is connected to digit line pairs (
606
and
608
). Also at time t
1
, a select signal Yj is activated, turning on transfer gate transistors (
616
and
618
) and connecting digit line pairs (
606
and
608
) to sense amplifier inputs (
614
-
c
and
614
-
d
). In this way, a memory cell data signal can be generated on digit line pairs (
606
and
608
) and supplied to a sense amplifier
614
. A memory cell data signal can result in the generation of a small differential voltage across the digit lines (
606
and
608
).
At time T
2
, the sense amplifier signal SE
1
is activated (driven high). The activation of the SE
1
signal activates the sense amplifier
614
. This can result in the digit line differential falling toward the low power supply voltage.
At time T
3
a digit line potential has been amplified by a sense amplifier
614
to a predetermined magnitude.
A drawback to an arrangement such as that set forth in
FIGS. 6 and 7
is the response of the sense amplifier
614
. Due to threshold voltages of inverter sections (
614
-
a
and
614
-
b
), when digit lines (
606
and
608
) are precharged to a high level, the time it may take sense voltage levels can add considerably to overall data sensing times.
It would be desirable to arrive at some way of improving the sense time of fast semiconductor devices. In particular it would be desirable to improve the sensing speed of a semiconductor device that includes a sense amplifier having an inverter section and one or more digit lines that are precharged to a high potential.
SUMMARY OF THE INVENTION
A memory device according to one embodiment of the present invention may include a pair of digit lines, a memory cell that places a data signal on the pair of digit lines, and a sense amplifier that can read data from the memory cell. A memory device may further include a switch circuit that connects at least one sense amplifier input to a predetermined potential to place the input at an intermediate potential with respect to sensed logic levels.
According to one aspect of the embodiments, the digit lines may be precharged to a first supply potential and a switch circuit can provide a connection to a second supply potential that is different from the first supply potential. The intermediate potential may be between the first supply potential and the second supply potential. A first supply potential may be a high power supply voltage. A second supply potential may be a low power supply voltage.
According to another aspect of the embodiments, the switch circuit may be activated prior to the sense amplifier, bringing digit lines to a potential that may allow for faster sensing.
According to another aspect of the embodiments, a switch circuit may be activated according to a timing signal. The timing signal may be a pulse of a predetermined duration.
According to another aspect of the embodiments, a switch circuit may include a NMOS transistor.
According to another aspect of the embodiments, a switch circuit may include a PMOS transistor.
According to another aspect of the embodiments, a switch circuit may include a bipolar transistor.
According to another aspect of the embodiments, a method of controlling a semiconductor storage device may include providing a semiconductor device with a pair of digit lines, a memory cell that supplies data signals to the digit lines, a sense amplifier that reads data from the memory cell, and a switch circuit connected to sense amplifier inputs.
Such a method may further include selecting the memory cell. The digit lines may then be pulled toward a first predetermined potential, and released from the first predetermined potential when they are about one half of a power supply voltage.
According to one aspect of the above control method embodiment, a sense amplifier can latch a data signal from a memory cell after the digit lines are about one half the power supply voltage.
REFERENCES:
patent: 4961168 (1990-10-01), Tran
patent: 5050127 (1991-09-01), Mitsumoto et al.
patent: 5566126 (1996-10-01), Yoshida
patent: 5835427 (1998-11-01), McClure
patent: 02-294991 (1990-05-01), None
patent: 08-007573 (1996-01-01), None
English Abstract of JP 02-294991 and 08-007573 noted above.
Copy of Japanese Patent Office Action dated Jul. 3, 2001 regarding corresponding foreign application.
English translation of indicated portions of above Japanese Patent Office Action.
Dinh Son T.
NEC Corporation
Walker Darryl G.
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