Semiconductor memory device and bit line sensing method thereof

Details Semiconductor memory device and bit line sensing method thereof Semiconductor memory device and bit line sensing method thereof

2002-11-08

2004-12-07

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S196000, C365S203000, C365S207000, C365S189090, C365S194000, C365S233100, C365S189070

Reexamination Certificate

active

06829189

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device and a bit line sensing method. More particularly, the present invention relates to a semiconductor memory device that may be operated at a low power voltage.
2. Description of the Related Art
In a semiconductor memory device, a charge transfer pre-sensing (CTPS) function is typically used to improve a sensing margin of a lower power voltage.
FIG. 1
illustrates a circuit diagram of a conventional semiconductor memory device having a charge transfer pre-sensing scheme. This conventional semiconductor memory device includes a cell bit line pre-charge circuit
10
, a PMOS sense amplifier
12
, a sense amplifier bit line pre-charge circuit
16
, an NMOS sense amplifier
18
, first and second bit line isolation circuits
14
and
20
, respectively, and memory cells MCi and MCj.
The memory cell MCi represents a representative memory cell among memory cells arranged in a memory cell array block BLK
1
among n-number of memory cell array blocks BLK
1
to BLKn. Similarly, memory cell MCj represents a representative memory cell among memory cells arranged in the memory cell array block BLK
2
. A capacitor Cb
1
represents a cell bit line load capacitor, and a capacitor Csa represents a sense amplifier bit line load capacitor.
NMOS transistors N
1
, N
2
and N
3
of the cell bit line pre-charge circuit
10
are turned on in response to a control signal BLPRE having a logic “high” level to pre-charge the cell bit line pair BLcelli and BLBcelli to a voltage Vcca/2. PMOS transistors P
1
and P
2
of the PMOS sense amplifier
12
are turned on in response to a voltage of the cell bit line pair BLBcelli and BLcelli having a logic “low” level to amplify a voltage of the bit line pair BLcelli and BLBcelli having a logic “high” level to a voltage Vcca. NMOS transistors N
4
and N
5
of the first bit line isolation circuit
14
are turned on in response to a control signal SG
1
to electrically connect the cell bit line pair BLcelli and BLBcelli to the sense amplifier bit line pair BLsa and BLBsa, respectively. NMOS transistors N
6
, N
7
and N
8
of the sense amplifier bit line pre-charge circuit
16
are turned on in response to a control signal SAPRE having a logic “high” level to pre-charge the sense amplifier bit line pair BLsa and BLBsa to a voltage Vcca. NMOS transistors N
9
and N
10
of the NMOS sense amplifier
18
are turned on in response to a voltage of the sense amplifier bit line pair BLsa and BLBsa having a logic “low” level to make the voltage of the sense amplifier bit line pair BLsa and BLBsa a ground voltage. NMOS transistors N
11
and N
12
of the second bit line isolation circuit
20
are turned on in response to a control signal SG
2
to electrically connect the cell bit line pair BLcellj and BLBcellj to the sense amplifier bit line pair BLsa and BLBsa, respectively.
Operation of the semiconductor memory device of
FIG. 1
is described below with reference to
FIG. 2
, in which a timing diagram illustrating an operation of the semiconductor memory device of
FIG. 1
is shown. In
FIG. 2
, a data is read from the memory cell array block BLK, and a cell array voltage Vcca is 0.8 volts.
A pre-charging operation is initiated with the application of the control signals BLPRE, SAPRE, SG
1
and SG
2
. The activating voltage level for SG
1
and SG
2
is 0 volts. The NMOS transistors N
4
and N
5
are turned off to electrically separate the sense amplifier bit line pair BLsa and BLBsa from the cell MCi bit line pair BLcelli and BLBcelli, and the NMOS transistors N
11
and N
12
are turned off to electrically separate the sense amplifier bit line pair BLsa and BLBsa from the cell MCj bit line pair BLcelli and BLBcelli. The NMOS transistors N
1
to N
3
are turned on to pre-charge the cell bit line pair BLcelli and BLBcelli to a voltage Vcca/2 (=0.4 volts). The NMOS transistors N
6
, N
7
and N
8
are turned on to pre-charge the sense amplifier bit line pair BLsa and BLBsa to a voltage Vcca(1+&ggr;) (=1.6 volts).
Then, when a read command is applied to select word line WLi, the NMOS transistor NM of the memory cell MCi connected to the word line WLi is turned on, and a charge sharing operation is performed between a capacitor C and the cell bit line pair BLcelli and BLBcelli. This causes a voltage difference &Dgr;VBLcell to occur between the cell bit line pair.
When the control signal SG
1
is activated with a voltage of 0.9 volts, the NMOS transistors N
4
and N
5
are turned on and a charge transfer operation is performed between the cell bit line pair BLcelli and BLBcelli and the sense amplifier bit line pair BLsa and BLBsa. Hence, a voltage of the sense amplifier bit line pair BLsa and BLBsa is lowered, and a voltage difference occurs between the sense amplifier bit line pair BLsa and BLBsa, as governed by the equation:
&Dgr;
VBLsa
(=&Dgr;
V
×(
Cb
1
+
Csa
)/
Csa
).  [1]
As the voltage of the sense amplifier bit line pair BLsa and BLBsa decreases, the voltage of the cell bit line pair BLcelli and BLBcelli increases, and the voltage difference between the cell bit line pair BLcelli and BLBcelli, &Dgr;VBLcelli, is steadily lowered to 0 volts. Thereafter, when the voltage difference &Dgr;VBLsa occurs between the sense amplifier bit line pair BLsa and BLBsa, the PMOS sense amplifier
12
and the NMOS sense amplifier
18
operate to amplify the voltage of the cell bit line BLcelli and the sense amplifier bit line BLsa to Vcca, and the voltage of the cell bit line BLBcelli, and the sense amplifier bit line BLBsa to 0 volts.
However, the semiconductor memory device of
FIG. 1
has a problem in that it is difficult to set a level of the control signal SG
1
, which is governed by the inequality [2]:
1
2
⁢
Vcca
⁢
(
1
+
1
1
+
Cb1
+
Cs
Cs
≤
VSG1
-
Vth
≤
Vcca
⁢
(
1
+
γ
)
⁢
Csa
+
(
1
2
⁢
Vcca
)
⁢
Cb1
Cb1
+
Cs
+
Csa
+
0.05
where VSG
1
denotes a voltage of the control signal SG
1
and Vth denotes a threshold voltage of the NMOS transistors N
4
and N
5
.
A left member of the inequality is a lower limit of a voltage of the control signal SG
1
, and a right member of the inequality is an upper limit of a voltage of the control signal SG
1
. A voltage of the control signal SG
1
is at least higher by a threshold voltage Vth than a data having a logic “high” level, and is at least lower by a threshold voltage Vth than a data having a logic “low” level. That is, the left member and the right member of the inequality are the upper limit and the lower limit, respectively, when NMOS transistors N
4
and N
5
operate in a saturation region rather than in a linear region to perform a charge transfer operation.
In order to increase a voltage margin of the control signal SG
1
, the pre-charge voltage has to be greater than a voltage Vcca with &ggr; having a value of about 1. Assume that the capacitor C has a capacitance of 20 fF, the capacitor Cb
1
has a capacitance of 120 fF, the voltage Vcca has a voltage of 0.8 volts, and a threshold voltage has a voltage of 0.4 volts. If the values are substituted in the inequality, the voltage VSG
1
of the control signal SG
1
is bounded by 0.85 volts or more and 0.95 volts or less. Thus, the voltage VSG
1
has a very small margin of 0.1 volts. Therefore, it is very difficult to accurately set a level of the control signal SG
1
.
In addition, the semiconductor memory device of
FIG. 1
has a problem in that the PMOS sense amplifier
12
is not shared between the respective memory cell array blocks but is separately configured, thereby increasing a layout area size. Furthermore, since the sense amplifier bit line pair BLsa and BLBsa have to be pre-charged to be higher than a voltage Vcca during the pre-charge operation, power consumption is high.
FIG. 3
illustrates a circuit diagram of another conventional semiconductor memory device having a charge transfer pre-sensing scheme. The semiconductor memory device of
FIG. 3
includes first and second bit lin

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