Semiconductor memory device and automatic bit line precharge met

Static information storage and retrieval – Read/write circuit – Precharge

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36523003, 36523006, G11C 700, G11C 800

Patent

active

057152039

ABSTRACT:
The present invention relates to a semiconductor memory device having a bit line precharge circuit which precharges bit lines forming a data transfer path coupled to cells. The memory device is further provided with a first control circuit which controls the bit line precharge circuit to precharge the bit lines in response to a bit line precharge request, and a second control circuit which recognizes a command input from outside and makes the bit line precharge request with respect to the first control circuit. The second control circuit accepts a selection of whether or not to request automatic precharge of the bit lines when making an entry to a burst mode even when a burst length is set to a full column, and makes the bit line precharge request with respect to the first control circuit so that the bit lines are precharged after the burst mode ends when an entry to the burst mode requests the automatic precharge.

REFERENCES:
patent: 5294342 (1994-03-01), Casper et al.
patent: 5416743 (1995-05-01), Allan et al.
patent: 5463590 (1995-10-01), Watanabe

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