Semiconductor memory device and a semiconductor integrated...

Details Semiconductor memory device and a semiconductor integrated... Semiconductor memory device and a semiconductor integrated...

2000-01-07

2001-09-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including level shift or pull-up circuit

C365S189050, C365S189060, C365S203000

Reexamination Certificate

active

06292408

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a semiconductor integrated circuit, and more particularly to a semiconductor memory device which converts write data provided from an external device into complementary data, and to a semiconductor integrated circuit having a plurality of data lines which are reset prior to transmission and a semiconductor integrated circuit which is provided with a clock signal having a predetermined phase difference with respect to a main clock signal.
A demand for a semiconductor memory device having low power consumption has been increased for extending a battery life of a portable device using semiconductor memory devices. Additionally, the demand has been also increased so as to maintain an amount of heat within an allowable range of a plastic package when the circuit scale is increased.
When data is transmitted through a data bus in the semiconductor memory device, an electric charge is provided to and removed from the data bus in the semiconductor memory device. The amount of electric charge is calculated by (voltage amplitude×capacity of data bus×number of switching operations×number of data buses).
In recent semiconductor integrated circuits, a width of a data bus has increased to 32 bits or 64 bits, and a signal frequency has increased to as high as 100 MHz. Additionally, since the data bus has a large capacity, a large power is consumed for transmission of data in the semiconductor integrated circuit. Accordingly, it is an important issue to reduce the power consumption of the data bus.
DESCRIPTION OF THE RELATED ART
FIG. 1
is a circuit diagram of a part of a conventional static random access memory (static RAM). In
FIG. 1
, the reference numeral
1
indicates a memory cell,
1
A and
1
B indicate data input/output nodes, and BL and /BL indicate bit lines.
The reference numeral
2
indicates a pMOS transistor having a 7-&mgr;m gate width. The pMOS transistor
2
corresponds to a loading element of the bit line BL. A source of the pMOS transistor
2
is connected to a VCC power source line
4
which provides a power source voltage VCC. A drain of the pMOS transistor is connected to the bit line BL.
The reference numeral
3
indicates a pMOS transistor having a gate width the same as that of the pMOS transistor
2
. The pMOS transistor
3
corresponds to a loading element of the bit line /BL. A source of the pMOS transistor
3
is connected to the VCC power source line
4
. A drain of the pMOS transistor
3
is connected to the bit line BL.
The reference numeral
5
indicates a write recovery circuit, and
6
indicates an inverter for inverting a write recovery signal WR which controls a write recovery operation. The write recovery signal WR is at a high logic level (H-level) during a write recovery period, and at a low logic level (L-level) during periods other than the write recovery period.
The reference numeral
7
indicates a pMOS transistor which is provided for pulling up the bit line BL. The pMOS transistor
7
which has a 18-&mgr;m gate width is provided for the bit line BL. A source of the pMOS transistor
7
is connected to the VCC power source line
4
. A drain of the pMOS transistor
7
is connected to the bit line BL. The pMOS transistor
7
is controlled to be turned on and off by an output of the inverter
6
.
The reference numeral
8
indicates a pMOS transistor which is provided for pulling up the bit line /BL. The pMOS transistor
8
has a gate width the same as that of the pMOS transistor
7
. A source of the pMOS transistor
8
is connected to the VCC power source line
4
. A drain of the pMOS transistor
8
is connected to the bit line /BL. The pMOS transistor
8
is controlled to be turned on and off by the output of the inverter
6
.
In the static RAM having the above-mentioned structure, the VCC power source voltage is provided to the bit lines BL and /BL via the pMOS transistors
2
and
3
, respectively. Thus, when the memory cell
1
is selected in a read cycle, one of the bit lines BL and /BL is maintained at the power source voltage VCC in accordance with read data from the memory cell
1
and the other one of the bit lines BL and /BL is set to a voltage slightly lower than the power source voltage VCC. Accordingly, a small voltage difference is generated between the bit lines BL and /BL, and is amplified by a sense amplifier (not shown in the figure).
On the other hand, when the memory cell
1
is selected in a write cycle, one of the bit lines BL and /BL is maintained at the power source voltage VCC in accordance with write data to the memory cell
1
and the other one of the bit lines BL and /BL is set to a ground level voltage (zero volts) so as to perform a write operation to the memory cell
1
.
FIG.2
is a waveform chart for explaining an operation of the write recovery circuit
5
.
FIG. 2
indicates changes in voltages at the bit lines BL and /BL and changes in the write recovery signal WR when the operation is shifted as write cycle→read cycle A→read cycle B.
When the operation is shifted from the read cycle A to the read cycle B, the power source voltage VCC is provided, for example, to the bit line BL and a voltage slightly lower than the power source voltage VCC is provided to the bit line /BL during the read cycle A. Thereafter, the power source voltage VCC is provided to the bit line /BL and a voltage slightly lower than the power source voltage VCC is provided to the bit line BL during the read cycle B. In this case, the voltage provided to the bit line /BL must be increased to the power source voltage VCC during the read cycle B. This operation can be done by the pMOS transistor
3
which is a loading element of the bit line /BL.
On the other hand, when the operation is shifted from the write cycle to the read cycle A, the power source voltage VCC is provided, for example, to the bit line /BL and the bit line BL is set to the ground voltage (zero volts) during the write cycle. Then, if the power source voltage VCC is provided to the bit line BL and a voltage slightly lower than the power source voltage VCC is provided to the bit line /BL during the read cycle A, the voltage provided to the bit line BL must be increased from zero volts to the power source voltage VCC during the read cycle A.
When this operation is performed by the pMOS transistor
2
which is a loading element of the bit line BL, the voltage at the bit line BL cannot be rapidly increased to the power source voltage VCC as indicated by a double dashed chain line in FIG.
2
. Accordingly, the small voltage difference due to the read data between the bit lines BL and /BL cannot be generated unless the period of the operation cycle is extended. Thus, a high-speed operation cannot be achieved.
In the above-mentioned static RAM, when a write cycle is shifted to a read cycle, the write recovery signal WR is set to the H-level during a predetermined period as a writer recovery period. The output of the inverter
6
is set to the L-level, and pMOS transistors
7
and
8
are turned on. When the bit line BL is at zero volts, the bit line BL is charged via the pMOS transistor
7
which has a greater gate width than that of the pMOS transistor
2
so that the voltage at the bit line BL is rapidly increased to the power source voltage VCC. When the bit line /BL is at zero volts, the bit line /BL is charged via the pMOS transistor
8
which, similarly, has a greater gate width than that of the pMOS transistor
3
so that the voltage of the bit line BL is rapidly increased to the power source voltage VCC.
In the static RAM, the pMOS transistor
8
, which is provided for the bit line /BL and does not need to be pulled up, is driven during the write recovery period. Thus, a discharge is made for a gate capacity of the pMOS transistor
8
, which does not need to be driven, during the write recovery period. Thereafter, when the write recovery period is terminated, a charge is performed for the gate capacity.
Since each of the pMOS transistors
7
and
8
, which are provid

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