Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-03-13
2007-03-13
Pert, Evan (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S401000, C257SE27099, C365S188000
Reexamination Certificate
active
10629733
ABSTRACT:
Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
REFERENCES:
patent: 5072286 (1991-12-01), Minami et al.
patent: 5132771 (1992-07-01), Yamanaka et al.
patent: 5239196 (1993-08-01), Ikeda et al.
patent: 5364810 (1994-11-01), Kosa et al.
patent: 5550396 (1996-08-01), Tsutsumi
patent: 6060723 (2000-05-01), Nakazato et al.
patent: 6740921 (2004-05-01), Matsuoka et al.
patent: 5062474 (1993-03-01), None
patent: 5-206394 (1993-08-01), None
patent: 5206394 (1993-08-01), None
patent: 6104405 (1994-04-01), None
patent: 8-88328 (1996-04-01), None
patent: 888328 (1996-04-01), None
patent: 11-87541 (1999-03-01), None
patent: 03019663 (2003-03-01), None
patent: WO 03019663 (2003-03-01), None
patent: 03036714 (2003-05-01), None
patent: WO 03036714 (2003-05-01), None
U.S. Appl. No. 10/465,550 Specification (pp. 77) and drawings (pp. 78).
H. Takato, et al., “High Performance CMOS Surrounding Gate Transistor (SGT) for Ultra High Density LSts”, 1988 IEEE, pp. 222-225.
Chakihara Hiraku
Mizuno Makoto
Moniwa Masahiro
Nishida Akio
Noguchi Mitsuhiro
Antonelli, Terry Stout and Kraus, LLP.
Hitachi Ulsi Systems Co., Ltd.
Pert Evan
LandOfFree
Semiconductor memory device and a method of manufacturing... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor memory device and a method of manufacturing..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device and a method of manufacturing... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3740837