Semiconductor memory device and a manufacturing method thereof

Details Semiconductor memory device and a manufacturing method thereof Semiconductor memory device and a manufacturing method thereof

1993-09-30

1995-01-31

Nguyen, Viet Q.

Static information storage and retrieval

Systems using particular element

Semiconductive

437 52, 257296, 257298, H01L 2702, H01L 2710

Patent

active

053863828

ABSTRACT:
A semiconductor memory device includes a cell array region and a peripheral circuit region, wherein a channel is formed to surround the cell array region, on a border region between the cell array region and peripheral circuit region. Also, a method for the semiconductor memory device is provided. Therefore, the conventional problem of degraded reliability of the conductive layer due to the step between the cell array region and peripheral circuit region, can be prevented. At the same time, the surface planarization of the peripheral circuit region can be attained.

REFERENCES:
patent: 4882289 (1989-11-01), Maunchi et al.
patent: 5171713 (1992-12-01), Matthews
patent: 5279983 (1994-01-01), Ahn
Kawanago et al., "3-Dimensional Stacked Capacitor-Cell for 16M and 64M Drams", IEDM, 1988, pp. 592-595.
Inoue et al., "A New Stacked Capacitor Cell With Thin Box Structured Storage Node", Extended Abstracts of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 141-144.
Inoue et al., "A Spread Stacked Capacitor (SSC) Cell for 64MBIT Drams", IEDM, 1989, pp. 31-34.
Wakamiya et al., "Novel Stacked Capacitor Cell for 64Mb Dram", LSI R&D Laboratory, Mitsubishi Electric Corp., pp. 69 and 70.

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