Semiconductor memory device allowing mounting of built-in...

Details Semiconductor memory device allowing mounting of built-in... Semiconductor memory device allowing mounting of built-in...

2001-01-11

2004-08-24

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000, C365S201000

Reexamination Certificate

active

06782498

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to semiconductor memory devices with built-in BIST Built In Self Test) circuits.
2. Description of the Background Art
A structure of semiconductor memory devices with built-in BIST circuits is known as a structure incorporating a tester function into a chip and allowing a test of the chip without the use of an expensive LSI tester.
The BIST circuit in the semiconductor memory device supplies as outputs a command and test data to a circuit to be tested according to a test pattern held in advance for performing a self test in response to an activation request. In addition, the BIST circuit generates an expected value of a response of the circuit to be tested to the test pattern, determines whether an output from the circuit to be tested matches with the expected value and outputs the result of the determination.
Here, in memory devices such as semiconductor memory devices or the like, an interface between the device and external devices must be considered. Particularly for general-purpose products, a common interface specification is usually determined.
The BIST circuit has a various advantages such as elimination of an expensive test device for the test of the device, reduction of the number of test signals supplied from an external source and ability of performing a so-called AT-SPEED test. When the BIST circuit is to be mounted particularly on a general-purpose memory device, however, a problem arises with regard to how to secure an interface between the BIST circuit and an internal circuit of the memory device in compliance with the commonly determined interface specification.
Japanese Patent Laying-Open No. 60-65360, for example, discloses a structure including a memory diagnostic control circuit inside which is functionally equivalent to the BIST circuit, however a description in detail is not provided as to how an interface between the BIST circuit and the internal circuit of the device is actually secured.
In addition,
FIG. 4
of Japanese Patent Laying-Open No. 10-134599 discloses, with regard to memory devices with BIST circuits, a structure in which a test input signal generated by a self-diagnostic circuit which is functionally equivalent to the BIST circuit and an input signal at a normal time are selectively supplied as an input to a semiconductor memory according to a test switching signal supplied as an input to a dedicated test switching pin. However, as the structure like this requires a dedicated input pin, it cannot be adopted under the general-purpose interface specification.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a structure of a semiconductor memory device allowing securing of an interface between a built-in BIST circuit and an internal circuit without an addition of a special interface specification.
In summary, the present invention is a semiconductor memory device operating in response to a plurality of command control signals and an address signal including a plurality of address bits, and includes a memory cell array, a plurality of external command terminals, a plurality of external address terminals, a self test circuit, a first input switching circuit, a second input switching circuit, a test mode circuit and a control circuit.
The memory cell array includes a plurality of memory cells arranged as a matrix. The plurality of external command terminals externally receives the plurality of command control signals. The plurality of external address terminals externally receives the plurality of address bits. The self test circuit operates at a time of test execution and supplies the plurality of command control signals and the plurality of address bits based on a predetermined test pattern. The first input switching circuit supplies a plurality of internal command control signals according to the plurality of command control signals received from the plurality of external command terminals or the plurality of command control signals received from the self test circuit. The second input switching circuit supplies an internal address signal having a plurality of address bits according to the plurality of address bits received from the plurality of external address terminals or the plurality of address bits received from the self test circuit. The test mode circuit determines an operation state of the self test circuit according to the plurality of internal command control signals and the internal address signal. The control circuit controls outputs of first and second input switching circuits according to the operation state of the self test circuit. The control circuit generates a command for the memory cell array according to the plurality of internal command control signals and the internal address signal.
Hence, a main advantage of the present invention lies in that a source of an input of the command control signal and the address signal to the control circuit can be switched according to the state of operation of the self test circuit between the external command terminal and the external address terminal and the self test circuit, whereby the semiconductor memory device can be operated in response to the output signal from the self test circuit during the test mode without the special interface for the external source.


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patent: 57-55598 (1982-04-01), None
patent: 59-168995 (1984-09-01), None
patent: 60-65360 (1985-04-01), None
patent: 61-67162 (1986-04-01), None
patent: 10-134599 (1998-05-01), None

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