Semiconductor memory device achieving faster operation based...

Details Semiconductor memory device achieving faster operation based... Semiconductor memory device achieving faster operation based...

1998-06-25

2001-12-11

Butler, Dennis M. (Department: 2182)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

C713S500000, C713S503000

Reexamination Certificate

active

06330682

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and particularly relates to adjustment of timings at which address signals and data signals are latched.
2. Description of the Related Art
FIG. 1
is a block diagram of a command-input and address-input portion of a related-art semiconductor device.
As shown in
FIG. 1
, command-input signals /CAS (column address strobe), /RAS (row address strobe), /CS (chip select), and /WE (write enable) are input to input buffers
201
through
204
. The input buffers
201
through
204
are current-mirror-type buffers, and produce a HIGH-level output or a LOW-level output depending on a comparison between an input signal and a reference voltage level.
The command signals output from the input buffers
201
through
204
are supplied to synchronization buffers
205
through
208
, respectively, where synchronization is established between the command signals and a clock signal CLK. The command signals in synchronism with the clock signal CLK are supplied from the synchronization buffers
205
through
208
to a command decoder
209
.
The command decoder
209
decodes the command signals /CAS, /RAS, /CS, and /WE so as to output command-decode signals. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and HIGH, respectively, for example, a data-read operation is selected, and the command-decode signals represent the data-read operation. When the command signals /CAS, /RAS, /CS, and /WE are LOW, HIGH, LOW, and LOW, respectively, for example, a data-write operation is selected, and the command-decode signals indicate this fact.
When either a data-write operation or a data-read operation is indicated, an address-input circuit
210
latches address signals at a timing triggered by the command-decode signals supplied from the command decoder
209
. The address latched by the address-input circuit
210
is supplied to internal circuits. A control circuit
211
controls the internal circuits so as to achieve the operation which is indicated by the command-decode signals supplied from the command decoder
209
. In
FIG. 1
, signal lines from the command decoder
209
to the address-input circuit
210
and the control circuit
211
are shown in a simplified manner. In actuality, a plurality of signal lines are provided for these paths.
The command decoder
209
is implemented by using a logic circuit of a relatively simple structure, but is designed to reduce an effect of skews between the command signals. Because of this, there is a problem in that a signal delay is relatively large in the command decoder
209
. Assume that a two-input NAND circuit is used in the command decoder
209
, and receives a first input signal and a second input signal, where the second signal is supposed to change from LOW to HIGH at the same timing at which the first signal changes from HIGH to LOW. If there is an unexpected delay in the change from HIGH to LOW in the first input signal, both signals maintain a HIGH level simultaneously during a short time period. The NAND circuit thus ends up outputting an erroneous signal level. In order to obviate this problem, a gate width of the transistors in the NAND circuit is made narrower, thereby slowing a change in the signal level. This prevents an erroneous signal level from appearing an output for a short time period.
When a signal delay at the command decoder
209
is elongated because of such a measure as described above to cope with signal skews, a timing at which the address-input circuit
210
latches the address signals is also delayed. Until the address signals are latched and stabilized, a data-write/read operation cannot be started. The delay in the command decoder
209
thus hinders an effort to increase operation speed of the semiconductor memory device.
Accordingly, there is a need for a semiconductor memory device which allows a timing of the address-signal input to be advanced in time so as to achieve high-speed operations.
Similar problems also exist with regard to timings of address-signal decoding, redundant checking, data-signal latching, and burst-length control.
Accordingly, there is a further need for a semiconductor memory device which advances these timings so as to achieve high-speed operations.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a semiconductor memory device which can satisfy the need described above.
It is another and more specific object of the present invention to provide a semiconductor memory device which allows a timing of the address-signal input to be advanced in time so as to achieve high-speed operations.
In order to achieve the above objects according to the present invention, a semiconductor memory device having an internal circuit includes a command decoder which decodes input-command signals to supply decoded-command signals, an address-latch-signal-generation circuit, operating faster than the command decoder, which decodes the input-command signals to supply an address-latch signal, a control circuit which controls the internal circuit based on the decoded-command signals, and an address-input circuit which latches an address signal in response to the address-latch signal.
In the device described above, the address-latch-signal-generation circuit is provided separately from the command decoder, and operates faster than the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to one aspect of the present invention, the semiconductor memory described above is such that the command decoder includes a logic circuit operating at a first speed, and the address-latch-signal-generation circuit includes a logic circuit operating at a second speed faster than the first speed.
In the device described above, an operation speed of transistors is faster in the address-latch-signal-generation circuit than in the command decoder. Therefore, the timing of the address-signal latching becomes earlier than when the command decoder indicates such a timing.
According to another aspect of the present invention, the semiconductor memory device described above further includes input buffers which respectively receive the input-command signals from an exterior of the semiconductor memory device, first synchronization buffers which respectively receive the input-command signals from the input buffers, and supply the input-command signals to the command decoder in synchronism with a clock signal, a second synchronization buffer which receives the address-latch signal from the address-latch-signal-generation circuit, and supplies the address-latch signal to the address-input circuit in synchronism with the clock signal, wherein the address-latch-signal-generation circuit receives the input-command signals directly from the input buffers.
In the device described above, when a timing to establish synchronization with the clock signal is used as a reference, a timing at which the address-latch signal is input to the address-input circuit is earlier than a timing at which the decoded-command signals are input to the control circuit.
According to another aspect of the present invention, the semiconductor memory device described above is such that the first speed is set such that skews are sufficiently removed from the input-command signals when the command decoder decodes the command-input signals.
In the device described above, anti-skew measures are taken in the command decoder, so that malfunction of the semiconductor memory device can be prevented.
According to another aspect of the present invention, the semiconductor memory device described above is such that the second speed is faster than such speed as at least required to sufficiently remove the skews.
In the device described above, the anti-skew measures are put in place for the command decoder, while no such measures are taken for the address-latch-signal-generation circuit, which is thus free from a spee

Affiliated with

Also associated with

Rating

Semiconductor memory device achieving faster operation based... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device achieving faster operation based..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device achieving faster operation based... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2581650