Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2002-12-13

2004-03-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S201000, C365S230030

Reexamination Certificate

active

06707733

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-381412, filed Dec. 14, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a defect rescuing circuit for setting plural types of defect rescue units whose sizes are different.
2. Description of the Related Art
As a memory cell of an EEPROM which electrically erases/rewrites data, for example, a nonvolatile memory cell MC having an NMOS transistor structure as shown in
FIG. 6
is used. A double well structure is formed in a p-type semiconductor substrate (Psub). An n-type Well region (Nwell) is formed in the double well structure and a p-type Well region (Pwell) is formed in the n-type well region (Nwell). An n-type diffusion layer forming a source (S) of the NMOS transistor and an n-type diffusion layer forming a drain (D) of the NMOS transistor are formed in the p-type well region (Pwell). A floating gate (FG) of the NMOS transistor and a control gate (CG) of the NMOS transistor are formed on the p-type well region (Pwell). The floating gate (FG) is formed of a polycrystalline silicon layer which is a first level layer and a control gate (CG) is formed of a polycrystalline silicon layer which is a second level layer. The floating gate (FG) and the control gate (CG) are separated by an insulating film formed therebetween.
In an actual EEPROM, a memory cell array comprises a plurality of memory cells MC arranged in a matrix formed in one well region.
FIG. 7
shows an equivalent circuit of a memory cell array having a NOR gate type structure. In the memory cell array, one of the memory cells MC is selected by a plurality of row lines (word lines) WL and a plurality of column lines (bit lines) BL. The plurality of row lines (word lines) WL are connected to the control gates CG of the respective memory cells MC and the plurality of column lines (bit lines) BL are connected to the drains D of the respective memory cells MC. The sources S and Nwell and Pwell of all the memory cells MC are commonly connected to a common source line SL.
Operation of the memory cell MC is as follows. Erasing of data is carried out by applying, for example, 10V to the sources (S), Nwell, and Pwell of all the memory cells MC in the cell array formed in one p-type well region, and by applying, for example, −7V to all the word lines WL. The bit lines BL are maintained in a floating state. In this manner, electrons in the floating gates (FG) of the memory cells MC are emitted in the channels by tunneling, so that the threshold voltages of the memory cells become low. This state is, for example, data “1” (erased state).
Writing of data is carried out by applying, for example, 9V to the selected word line WL, and by applying, for example, 5V to the selected bit line BL. The source line SL is set to 0V. At this time, in the selected memory cell MC, electrons are injected in the floating gate (FG) due to hot electron injection, so that the threshold voltage of the selected memory cell becomes high. This state is data “0” (written state).
Reading of data carried out by applying a read voltage of, for example, about 5V to the selected word line WL. The bit line BLK is set to a low voltage of, for example, about 0.7V. The source line is set to 0V. At this time, when the selected memory cell is “0” (written state), an electric current does not flow because the memory cell is not turned on. When the selected memory cell is “1” (erased state), the memory cell is turned on, and an electric current of about 40 &mgr;A flows through the selected memory cell. Reading is carried out by amplifying the amplitude of the electric current by a sense amplifier circuit.
In such an EEPROM, defective cells may exist in the memory cell array due to problems (dust or the like) in manufacturing. Even if there are some defective cells, in order to make the memory cell array to a good product, various defect rescuing circuits (redundancy circuits) for rescuing defective cells are provided in the EEPROM. For example, a rescue in units of columns (column redundancy) is carried out with respect to a short-circuiting between the bit lines or a memory cell defect. A block rescue (block redundancy) is carried out in data erasing units with respect to a short-circuiting between the word lines and the source lines (source/P-Well or the like), because the short-circuiting between the word lines and the source lines is a detect in all the memory cells in the block in which the p-type well is commonly used, which is a data erasing unit.
FIG. 8
shows a relationship between the column rescue and the block rescue described above. As shown in
FIG. 8
, a redundancy column cell array for column rescue is provided in each of the plurality of normal cell blocks (cores). It is possible to carry out a column replacement corresponding to a defective bit line denoted by an x mark by using the redundancy column cell array. Also, a redundancy cell block (core) is provided with respect to defects of the normal cell blocks. It is possible to carry out a block replacement for a block defect denoted by an x mark, such as a word line short-circuiting with a source line, by using the redundancy cell block.
Specifically, in order to carry out defect rescue, testing of a memory chip is carried out, and a defect address is programmed in a defect address memory circuit in the chip on the basis of the test results. When the defect address memory circuit is configured by using a fuse, for example, a laser fusing type fuse, because the test process and the fuse circuit programming process by laser blow are completely separate, then the fuse circuit programming must be carried out after all the tests are completed.
However, in a case of an EEPROM, a test sequence is possible in which the defect address is sequentially programmed each time a defect is found in the test process, by using, as a memory element, a memory cell which is the same as the memory cell used for the EEPROM cell array in a defect address memory circuit. This is the reason that writing of the defect address can be carried out by using the test circuit as it is. A test time can be shortened by using such a test sequence. The reason is as follows. Even when a defective area is found in the EEPROM, if an attempt is made to continue the test as is up to the time when all the test results are obtained, a situation arises in which, for example, the writing operation never finishes in the defective area, so that it takes a large number of time for the test. When a sequential defect replacement control, in which the defect address is programmed immediately after a defect is found, is carried out, such a situation can be prevented, so that the test time can be shortened.
However, in the EEPROM, when a method is employed in which two types of defect rescue circuits such as a column redundancy circuit and a block redundancy circuit are loaded and a defect address is sequentially programmed in the test process, there is a problem such as follows. There is the possibility that a situation will arise in which a bit line defect is found in a given block, and a word line of the block which has been already column-relieved becomes defective in the test process after the column rescue is carried out. In this way, it is assumed that, when the rescue regions of the column rescue and the block rescue overlap, assuming that the defective column replacement in a defective block which is to be relieved is valid in the redundancy block, in the case where a defective column is further found in the redundancy block, there is the possibility that there will be no margin to carry out a defective column rescue.
For example, it is assumed that two sets of column rescue set are provided in each of the blocks. Assuming that column defects of the two sets exist in a main body block (normal cell block) before block r

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