Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2003-05-28

2004-10-05

Lam, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S210130

Reexamination Certificate

active

06801464

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly to an improvement to a semiconductor memory device, which can switch between a mode of reading word data and a mode of reading byte data. For example, this semiconductor memory device is applied to a NOR-type flash memory.
2. Description of the Related Art
There is known a NOR-type flash memory, which can switch between a mode of reading word data (WORD read mode) and a mode of reading byte data (BYTE read mode).
FIG. 10
is a circuit diagram showing a part of a conventional NOR-type flash memory of this kind.
As shown in
FIG. 10
, a data line array
6
is connected to a memory cell array
5
. The data line array
6
includes data lines D
0
, D
8
, D
1
, D
9
, . . . , D
7
, and D
15
(D
2
to D
7
and D
10
to D
15
are not shown) of 16 bits constituting word data. The 16 bit data lines D
0
to D
15
are arranged such that data lines D
0
, D
1
, . . . , and D
7
of the lower order 8 bits and data lines D
8
, D
9
, . . . , and D
15
of the higher order 8 bits are alternately disposed one by one.
The 16 bit data lines D
0
to D
15
are respectively connected to
16
sense amplifiers (S/A) S
0
, S
8
, S
1
, S
9
, . . . , S
7
, and S
15
(S
2
to S
7
and S
10
to S
15
are not shown), through 16 transistors T
0
, T
8
, T
1
, T
9
, . . . , T
7
, and T
15
(T
2
to T
7
and T
10
to T
15
are not shown). The higher order 8 bit data lines D
8
to D
15
are also respectively connected to the lower order
8
sense amplifiers S
0
to S
7
, through
8
transistors TA
8
to TA
15
(TA
10
to TA
15
are not shown).
In the WORD read mode, when data is read, the 16 bit data lines D
0
to D
15
are selected and charged all together. On the other hand, in the BYTE read mode, the lower order 8 bit data lines D
0
to D
7
or the higher order 8 bit data lines D
8
to D
15
are selected and charged. At this time, the non-selected higher order 8 bit data lines D
8
to D
15
or the non-selected lower order 8 bit data lines D
0
to D
7
are set at the ground potential.
As described later, the present inventor has found that the conventional NOR-type flash memory shown in
FIG. 10
causes a problem in that the data read speed in the BYTE read mode is lower than that in the WORD read mode.
BRIEF SUMMARY OF THE INVENTION
According to a first aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array;
a data line array connected to the memory cell array, and comprising 16 bit data lines for 16 bits constituting word data, the 16 bit data lines being arranged such that a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are alternately disposed one line by one line;
a read circuit configured to perform selection of the data lines, and charge selected data lines to read data, the read circuit being arranged to select and charge all the 16 bit data lines when reading data in a word data read mode, and to select and charge one of the first and second groups when reading data in a byte data read mode; and
a non-selection-side charge circuit configured to select and charge non-selected data lines, which belong to the other of the first and second groups not selected by the read circuit when reading data in the byte data read mode.
According to a second aspect of the present invention, there is provided a semiconductor memory device comprising:
a memory cell array;
a data line array connected to the memory cell array, and comprising 16 bit data lines for 16 bits constituting word data, the 16 bit data lines being arranged such that a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are disposed adjacent to each other group by group;
an intermediate dummy data line extending in parallel with the data lines in a boundary region between the first group and the second group;
a read circuit configured to perform selection of the data lines, and charge selected data lines to read data, the read circuit being arranged to select and charge all the 16 bit data lines when reading data in a word data read mode, and to select and charge one of the first and second groups when reading data in a byte data read mode; and
a first dummy-side charge circuit configured to charge the intermediate dummy data line when reading data in the word data read mode and the byte data read mode.


REFERENCES:
patent: 6208571 (2001-03-01), Ikeda et al.
patent: 6324112 (2001-11-01), Fournel

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