Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2002-05-15
2004-04-13
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230030, C365S230080
Reexamination Certificate
active
06721209
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memories, and more particularly, to an output circuit of sense amplifiers. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for rapidly transferring data from sense amplifiers to an output-buffer.
2. Discussion of the Related Art
With the higher integration and increased capacity of semiconductor memories, high-speed processing of semiconductor memory systems is required.
Accordingly, for high speed memories, it is desirable that each of the following constituent components of the memory cycle time be minimized as much as possible; clock-to-wordline selection, cell-to-sense amplifier, and sense amp-to-output.
The teachings of the present invention are particularly directed to reducing the time delay involved in the sense amp-to-output portion of the cycle time.
The sense amplifier is usually provided as a differential sense amplifier, with each of the memory cells providing both a data signal and a data-bar signal on the complementary bitlines associated with each column.
And, the sense amplifier coupled to the two complementary bitlines senses the differential voltage between the two bitlines, and the sensed difference is indicated by the sense amplifier as the different logic states of “0” and “1”.
A related art semiconductor memory device will now be described with reference to the accompanying drawings.
FIG. 1
is a block diagram illustrating a related art semiconductor memory device.
As shown in
FIG. 1
, the related art semiconductor memory device includes a plurality of sense amplifiers
2
coupled to each of the memory cell blocks. The sense amplifiers amplify the data of the bitlines disposed in the memory cell blocks. An output-buffer
4
is coupled to a common output-line of the sense amplifiers to transfer the data of a cell block
1
, as selected by an input address, to another device.
A pair of complementary bitlines, which are connected to the sense amplifier, are disposed in a sense amplifier block operable with the memory cell blocks. A plurality of sense amplifiers are accordingly provided for each memory cell. And, each sense amplifier is operable to sense the output of a given column.
The operation of the aforementioned related art semiconductor memory device will be described now. In operation, prior to activating the memory cells, the bitlines are precharged and equalized to a common value.
Once a particular row and column are selected, the memory cell associated therewith is activated such that it pulls one of the data lines toward ground, with the other data line remaining at the precharged level. The sense amplifier coupled to the two complementary bitlines senses the difference between the two bitlines. The sensed difference is indicated by the sense amplifier as the different logic states of “0” and “1”. Next, the output-buffer
4
, coupled to the common output-line of the sense amplifiers, transfers the data of sense amplifiers to the other device.
The related art semiconductor memory device, discussed above, has several drawbacks. A common output-line between an output-buffer and sense amplifiers has a significant delay in transferring the data from sense amplifiers to the output-buffer. Such delay is not desirable in many high-speed applications.
Further, in multi-bank memory architectures, prevalent in certain applications, the signal path between the sense amplifiers and a common output-line is not only variable but traverses longer distances as well.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a semiconductor memory device that substantially obviates one or more drawbacks, limitations, or disadvantages of the related art.
An object of the present invention is to provide a semiconductor memory device which has two common output-lines so as to rapidly transfer data values on a pair of bitlines.
In a presently preferred exemplary embodiment of the present invention, two common output-lines selectively are connected to a output-buffer according to a memory cell block. The data values on a pair of bitlines are transferred through a common output-line, selected by an input signal, to an output-buffer.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof, as well as the appended drawings.
To achieve these objects and other advantages, in accordance with the purpose of the invention, as embodied and broadly described herein, a semiconductor memory device includes a plurality of sense amplifiers respectively connected to a plurality of cell blocks, a first common output-line and a second common output-line transferring the data of the sense amplifiers into two parts according to the cell blocks, and a loading selection circuit selectively loading two common output-lines so as to transfer the data of a selected sense amplifier.
It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5923607 (1999-07-01), Suh
patent: 6166967 (2000-12-01), Do
patent: 6278650 (2001-08-01), Kang
patent: 6327214 (2001-12-01), Yoon et al.
patent: 6331955 (2001-12-01), Shin et al.
patent: 6337826 (2002-01-01), Imai et al.
patent: 6396766 (2002-05-01), Lee
Hynix / Semiconductor Inc.
Phan Trong
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