Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-10-23

2003-02-04

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230010

Reexamination Certificate

active

06515924

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device reducing power consumption by reducing signal lines to bank and preventing unnecessary operations of predecoder that is possible by interrupting signals generated from global area in a termination of CAS operation according to precharge interrupt command, during CAS access.
2. Description of the Related Art
FIG. 1
is a block diagram of semiconductor memory device related to interrupt when a conventional precharge signal is generated.
As shown in
FIG. 1
, it comprises a command buffer unit
1
for inputting rasb, casb and web of TTL level and for buffering them to CMOS level; a bank address buffer unit
2
for buffering bank address signal badd<i> of TTL level to CMOS level; a cas enable bank signal generating unit
3
for generating cas enable bank signal casen_ba<i> indicating bank wherein CAS command is performing; and a precharge interrupt signal generating unit
4
for inputting and combining output signals rasx, casz, wex of the command buffer unit
1
and for selecting bank of precharge command inputted by receiving output signal bat<i> of the bank address buffer unit
2
and if the cas enable bank signal casen_ba<i> corresponds to the bank of inputted precharge command, finally for generating precharge interrupt signal pcgterm to the corresponding bank
5
_n.
According to the conventional precharge interrupt, output signals of command buffer unit
1
rasx, casz, wex are combined in the precharge interrupt signal generating unit
4
and output signal bat<i> of the bank address buffer unit
2
is received to select bank of precharge command having the inputted bank address.
And, cas enable bank signal casen_ba<i> indicating bank wherein CAS command is performing is received and then, if the bank of inputted precharge command corresponds to the cas enable bank signal casen_ba<i> , precharge interrupt signal pcgterm is generated, thereby disabling column selection signal (in read) enabled in the corresponding bank or signal transmitted from global input/output line to data bus line of core (in write) in the corresponding clock.
However, according to the conventional semiconductor memory device, it is difficult for the precharge interrupt signal pcgterm to cover all the banks and therefore, signals are locally generated in each bank. As a result, the number of signal lines is increased from global area to local area and accordingly power consumption is also increased since the interrupted signals are almost in final step of cell access.
SUMMARY OF THE INVENTION
Therefore, the present invention has been made to solve the above problems and the object of the present invention is to provide a semiconductor memory device reducing power consumption by reducing signal lines to bank and preventing unnecessary operations of predecoder that is possible by minimizing delay time from buffer to master clock latch and interrupt inner command enable, thereby performing interrupt to predecoder strobe signal.
In order to accomplish the above object, the present invention comprises: a command buffer unit for inputting rasb, casb and web of TTL level and then buffering them to CMOS level; a bank address buffer unit for buffering bank address signal of TTL level to CMOS level; a cas enable bank signal generating unit for generating cas enable bank signal indicating enabled bank wherein the CAS is being performed; a precharge interrupt signal generating unit for combining output signals of the command buffer unit to detect precharge command and for comparing output signal of the bank address buffer unit and the inputted enable bank signal and if enabled bank corresponds to the bank selected by detected precharge command, for generating precharge interrupt signals and latching the generated precharge interrupt signals to master clock and finally outputting the signals; and a predecoder strobe signal generating unit for generating strobe signals operating predecoder to select bank by external cas or internal cas, the operations being controlled by the precharge interrupt signal.
And, the precharge interrupt signal generating unit comprises: a command decoding unit for decoding output signals of the command buffer unit; a bank decoding unit for comparing the output signal of bank address buffer unit and the cas enable bank signal and then for outputting signals indicating whether the enabled bank corresponds to the bank selected by detected precharge command; an enable signal generating unit for generating enable signal by using the output signals of the bank decoding unit according to output signals of the command decoding unit; and a latch unit for latching the enable signal to master clock and then for outputting precharge interrupt signal.
According to the above invention, precharge interrupt internal command is generated by using delay time for setup/hold time and then the signal is synchronized to internal clock, thereby terminating enable time of interrupt command at the beginning of CAS operation. Therefore, special time of CAS path is interrupted in global area, thereby reducing circuit area and preventing unnecessary circuit operations. As a result, it is effective in saving power consumption.


REFERENCES:
patent: 6310823 (2001-10-01), June

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