Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-28

2003-04-08

Phan, Trong (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S194000

Reexamination Certificate

active

06545922

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a dynamic random access memory, and particularly it relates to a semiconductor memory device with an accelerated operating speed.
2. Description of the Related Art
Conventional semiconductor memory devices such as a synchronous dynamic random access memory (SDRAM) are generally provided with a pre-charge circuit for pre-charging of I/O lines to which a plurality of bit lines pairs connected to memory cells are connected via a column selecting circuit. The pre-charge circuit used here adjusts the I/O lines to a prescribed potential for reading and writing of data, and it accelerates data reading and writing while preventing write and read errors.
FIG. 1
is a circuit diagram of a pre-charge circuit in a conventional semiconductor memory device.
In the pre-charge circuit
101
of a conventional semiconductor memory device there are provided two P-channel transistors Tr
101
a
and Tr
101
b
with their drains connected to I/O lines IOT and ION, respectively. A constant voltage Vc is supplied to the sources of the transistors Tr
101
a
and Tr
101
b,
and a pre-charge control signal PIO is supplied to each gate. During pre-charge, both the transistors Tr
101
a
and Tr
101
b
are switched on, and the potentials of the I/O lines IOT and ION become the constant voltage Vc. A design includes an equalizing transistor provided in the pre-charge circuit, with the two I/O lines IOT and ION short-circuited by the equalizing transistor during pre-charge, and adjusted to be at the same potential (balance level).
Operation of a conventional semiconductor device with a pre-charge circuit having that construction will now be explained. FIG.
2
A and
FIG. 2B
are schematics showing the operation of a conventional semiconductor memory device, where
FIG. 2A
is a timing chart for a case where the constant voltage Vc, i.e. balance level (Vcc/2<Vc
1
(=Vc)<Vcc) is high (hereinafter, first prior art), and
FIG. 2B
is a timing charge for a case where the constant voltage Vc
2
is ½ of the power voltage Vcc (hereinafter, second prior art). Here, the voltage Vcc is a power voltage supplied to the I/O circuit (not shown) connected to the pre-charge circuit. “Balance level” refers to a potential supplied to the I/O lines IOT and ION through each of the transistors Tr
101
a
and Tr
101
b,
or a potential of the I/O lines IOT and ION that converge when the two I/O lines IOT and ION are short-circuited by the equalizing transistor (not shown).
As shown in
FIG. 2A
, when the constant voltage Vc is set to satisfy Vcc/2<Vc
1
<Vcc (first prior art), the pre-charge control signal PIO is high during pre-charge before writing and reading, and the I/O lines IOT and ION are pre-charged to the voltage Vcl.
Next, when the pre-charge control signal PIO falls to begin writing or reading, the potential of the I/O lines IOT and ION is dragged to the potential of the bit line pairs connected to the memory cells composing a column selected by an address signal. As a result, the potential of the I/O line IOT increases (or decreases) and the potential of the I/O line ION decreases (or increases) in response to the read/written data. That is, a signal fed to the I/O line IOT and a signal fed to the I/O line ION are in a complementary relationship. If the operation at that time is data writing, a written signal is amplified by a write amplifier (not shown), and therefore the increase and decrease of each potential is large. Then, the potential of one I/O line converges to the internal power voltage Vcc, and the potential of the other I/O line converges to the ground potential GND.
On the other hand, if the operation is data reading, bit lines pairs of a DRAM are normally pre-charged to Vcc/2, and immediately after reading the bit line pairs undergo spreading of a potential difference centered on Vcc/2 in response to the read data. However, since amplification by a sense amplifier (not shown) of the differential potential between the bit line pairs is insufficient, the difference between the potential of one bit line pair and the potential of the I/O line IOT (or ION) is small and the increase (or decrease) of the potential of the I/O line IOT (or ION) is small. In contrast, since the voltage Vc
1
at the pre-charge level is higher than Vcc/2, the difference between the potential of the other bit line and the potential of the I/O line ION (or IOT) is large. Therefore, the potential of the I/O line ION (or IOT) undergoes a large decrease (or increase). It is therefore possible to obtain a sufficient differential potential for the I/O lines IOT and ION. This is because the relationship between the voltage between the gate-source and the drain current is a square relationship, and therefore a large potential difference between the gate-source results in a greater change in the drain current.
When the pre-charge control signal PIO rises next, the I/O lines IOT and ION are pre-charged to voltage Vc
1
. The data writing and reading and the pre-charging are then carried out alternately in synchronization with the rise and fall of the pre-charge control signal PIO. Upon completion of reading and writing, the pre-charge control signal PIO is fixed high.
On the other hand, when the constant voltage Vc is set to the voltage Vc
2
which is Vcc/2, as shown in
FIG. 2B
(second prior art), the pre-charge control signal PIO is high during pre-charge before writing and reading, and the IO lines IOT and ION are pre-charged to the voltage Vc
2
.
Next, when the pre-charge control signal PIO falls to begin writing or reading, the potential of the I/O lines IOT and ION is dragged to the potential of the bit line pairs connected to the memory cells composing a column selected by an address signal. As a result, the potential of the I/O line IOT increases (or decreases) and the potential of the I/O line ION decreases (or increases) in response to the read/write data. If the operation at that time is data writing, a written signal is amplified by the write amplifier (not shown), and therefore the increase and decrease of each potential is large. Then, the potential of one I/O line IOT or ION converges to the internal power voltage Vcc, and the potential of the other I/O line ION or IOT coverages to the ground potential GND. On the other hand, if the operation is data reading, the sense amplification by the sense amplifier (not shown) of the differential potential between the bit line pairs is insufficient, the difference between the potential of both bit lines and the potential of the I/O lines IOT and ION is small and the increase of the potential of the I/O lines IOT and ION is small.
When the pre-charge control signal PIO rises next, the I/O lines IOT and ION are pre-charged to voltage Vc
2
. At this time, since the pre-charge level is set to Vcc/2, the potential of the I/O lines IOT and ION rapidly reaches the voltage Vc
2
. The data writing and reading and the pre-charging are then carried out alternately in synchronization with the rise and fall of the pre-charge control signal PIO. Upon completion of reading and writing, the pre-charge control signal PIO is fixed high.
However, in the semiconductor memory device of the first prior are explained above, the constant voltage Vc is set to the voltage Vc
1
(Vcc/2<Vc
1
<Vcc), and therefore upon pre-charging of the I/O line IOT or ION switched to the GND side immediately after a wiring operation, time is required to restore it to the pre-charge level Vc
1
. Because of the long restoration time tb, the period of activation of the pre-charge control signal PIO (the high period in
FIG. 2A
) must be set longer, and thus the time for a single cycle tck for the pre-charge control signal PIO must be set longer.
Conversely, as in second prior art, the problem when the constant voltage Vc is set to voltage Vc
2
(Vcc/2) is as follows. When a row address is sent from the outside to the semiconductor memory device, one word line is activated and data stor

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