Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-08-08

2003-05-20

Mai, Son (Department: 2818)

Static information storage and retrieval

Read/write circuit

Precharge

C365S205000, C365S208000, C365S210130

Reexamination Certificate

active

06567326

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-241478, filed Aug. 9, 2000, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device.
2. Description of the Related Art
FIG. 15
is a circuit diagram showing a conventional semiconductor memory device.
As shown in
FIG. 15
, in the conventional memory device, a word line WL (WL
0
or WL
1
) and two bit lines BL (BL
0
and BL
1
) are independently connected to a memory cell (memory element).
A data read circuit is connected between two bit lines BL
0
and BL
1
. A sense amplification circuit (sense AMP. circuit) of a differential amplification type for differential-amplifying potential difference between two bit lines BL
0
and BL
1
is used in the Data Read Circuit.
An example of the memory cell is a SRAM cell. The SRAM cell includes, for example, two inverters that are connected to each other in a cross-coupled manner, that is, a latch circuit and two N-channel type MOSFETs that connect the latch circuit to the bit lines BL
0
and BL
1
in accordance with a potential of the word line WL. Thus, when the word line is activated, the bit lines BL
0
and BL
1
are electrically connected to the memory cell and a charge can be moved mutually in such a manner that from the bit lines BL
0
and BL
1
to the memory cell, or from the memory cell to the bit lines BL
0
and BL
1
. A drain of P-channel type MOSFETs whose gate receives a pre-charge signal and whose source receives a fixed electric potential is connected to the bit lines BL
0
and BL
1
. The P-channel type MOSFETs constitute a pre-charge circuit and used for pre-charge operation to be described later.
The sense AMP, circuit includes the latch circuit. The N-channel type MOSFET that is connected to earthed electric potential in accordance with a sense AMP. enable signal (S/A enable signal) and a pair of the P-channel type MOSFETs that are connected to the bit lines BL
0
and BL
1
in accordance with the S/A enable signal are connected to the latch circuit. Accordingly, when the S/A enable signal is activated, the latch circuit is connected to the earthed electric potential and disconnected from the bit lines BL
0
and BL
1
. At the timing when the S/A enable signal is activated, a slight amount of potential difference at the relevant time between the bit lines BL
0
and BL
1
is detected and the latch circuit amplifies the potential difference to a potential difference of CMOS level.
Next, operation of the conventional memory device will be described.
FIG. 16
is an operation waveform chart showing operation of the conventional memory device.
As shown in
FIG. 16
, in general, each electric potential of the bit lines BL
0
and BL
1
is set at a predetermined value (In
FIG. 16
, “HIGH” level is adopted.), before starting read/writing operation.
In the read operation, when the word line WL is activated, the memory cell is connected to the bit lines BL
0
and BL
1
. Electric potential of one bit line declines gradually in accordance with data stored in the latch circuit and a potential of the other bit line maintains “HIGH” level. The potential difference between the bit lines BL
0
and BL
1
is amplified by the sense AMP. circuit and output. After that, the word line WL is deactivated and the memory cell is disconnected from the bit lines BL
0
and BL
1
. When a pre-charge signal comes to “LOW” level, each electric potential of bit lines BL
0
and BL
1
is changed to “HIGH” level by the pre-charge circuit. This process is called pre-charge.
In the writing operation, the word line WL is activated and the memory cell is connected to the bit lines BL
0
and BL
1
. Furthermore, when a write enable signal is activated, the potential of one bit line is changed to “Low” level by a data write circuit and the potential of the other bit line maintains “HIGH” level. Accordingly, data is written in the memory cell. After that, the word line WL is deactivated and each potential of the bit lines BL
0
and BL
1
changes to “HIGH” level (pre-charge) in the same manner as the read operation.
As described above, the pre-charge is necessary after the read/write operation and plenty of time is spend on the pre-charge, in fact. A great deal of time required for the pre-charge is particularly necessary when the pre-charge is carried out after writing data with the bit line driven to “LOW” level and the read operation is carried out immediately after the pre-charge.
In this case, since the potential of the bit line drops to “low” level first and then changes to “HIGH” level, the voltage varies largely and accordingly plenty of transition time is required.
Additionally, in the read operation, the sense AMP. circuit detects a very slight amount of potential difference between the bit lines BL
0
and BL
1
. Therefore, when the read operation is started in an imperfect pre-charge state, possibility of causing malfunction is increased. For this reason, the read operation must be waited until the electric potential of the bit lines completely comes to “HIGH” level.
A cycle of a clock cannot be shortened less than time for a series of the above operation, that is, time required from the write operation to completion the pre-charge, or from the read operation to completion of the pre-charge. Thus, operation frequency of the conventional memory device is rate-limited.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to a first embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a first amplification circuit configured to amplify a potential of the first bit line; and a second amplification circuit configured to amplify a potential of the second bit line, the second amplification circuit being inactive when the first amplification circuit is active and being active when the first amplification circuit is inactive, in read operation.
A semiconductor device according to a second embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a amplification circuit configured to amplify a potential of the first bit line and a potential of the second bit line; and a multiplexer which selects the first bit line or the second bit line and electrically couples a selected bit line to the amplification circuit.
A semiconductor device according to a third embodiment of the present invention comprises: a first bit line; a second bit line; a memory cell electrically coupled to the first bit line and the second bit line; a first amplification circuit configured to amplify a potential of the first bit line; a second amplification circuit configured to amplify a potential of the second bit line; and a pre-charge circuit configured to pre-charge the first and second bit lines, the pre-charge circuit pre-charging the second bit line when the first amplification circuit is active, and pre-charging the first bit line when the second amplification circuit is active.


REFERENCES:
patent: 5034923 (1991-07-01), Kuo et al.
patent: 5065363 (1991-11-01), Sato et al.
patent: 5257236 (1993-10-01), Sharp
patent: 5265047 (1993-11-01), Leung et al.
patent: 5317537 (1994-05-01), Shinagawa et al.
patent: 5815432 (1998-09-01), Naffziger et al.
patent: 6166946 (2000-12-01), Naffziger
patent: 6181608 (2001-01-01), Keshavarzi et al.

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