Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1998-12-07

2002-10-29

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

Reexamination Certificate

active

06473873

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention generally relates to semiconductor memory devices, and in particular large-capacity semiconductor memory devices incorporating microelements.
2. Description of the Related Art
The recent development in semiconductor technologies has enabled the capacity of DRAMs to increase fourfold every three years. The market supply of 16 Mbit DRAMs has practically reached its peak, and 64 Mbit DRAMs have begun to become available on the market. On the research and development end, 256 Mbit to 1 Gbit DRAMs are under development.
Irrespective of the capacity of DRAMs, it is essential to subject them to tests for distinguishing those which are satisfactory from those which are defective.
Among others, the following problems (i) and (ii) need to be solved in connection with such testing of large capacity DRAMs:
i) Reduction in test mode time
More time will be required for the test mode operation as the storage capacity of DRAMs increases. However, it is preferable to minimize the test mode time.
ii) Improvement in test accuracy
As a method for testing DRAMs, for example, a so-called parallel test has been proposed (see “92.9 HITACHI IC MEMORY DATABOOK p. 639, Internal 16 bit parallel testing function”; “PARALLEL TESTING TECHNIQUES SUITABLE FOR SUPER LARGE CAPACITY MEMORIES, Matsumura et al., ICD87-75 pp. 41-46”; and “A 45 ns 64 Mb DRAM WITH A MERGED MATCH-LINE TEST ARCHITECTURE, Shigeru, Mori., et al., 1991 IEEE ISSCC pp. 110-111”).
In a parallel test, for example, the same data is written to a plurality of memory cells which are coupled to the same word line in a DRAM so as to examine whether or not all of the values output from a plurality of bit lines corresponding to the memory cells are the same. Such a test may be performed by supplying the values output from the plurality of bit lines to EXOR circuits, for example. However, this technique has a problem in that, assuming that data “1” is written to the plurality of memory cells coupled to the same word line, if all the memory cells output “0”, the EXOR circuits will erroneously determine such a DRAM as satisfactory.
Thus, a parallel test may be utilized as a screening test, but does not provide sufficient accuracy.
SUMMARY OF THE INVENTION
A semiconductor memory device according to the present invention includes: a memory block including a plurality of memory cells; and a test pattern generation circuit for generating at least one test pattern for use in testing the memory block, wherein a first bus line for coupling the memory block and the test pattern generation circuit has a larger width than that of a second bus line for coupling the memory block to the exterior of the semiconductor memory device.
In one embodiment of the invention, the test pattern generation circuit includes a storage section for storing a plurality of test patterns, and one of the plurality of test patterns is output in accordance with an address signal received by the test pattern generation circuit.
In another embodiment of the invention, the semiconductor memory device includes a comparison circuit for comparing a test pattern which is read from the memory block against a test pattern which is generated by the test pattern generation circuit.
In still another embodiment of the invention, the semiconductor memory device includes a switching circuit for selectively outputting the test pattern which is generated by the test pattern generation circuit to one of the memory block and the comparison circuit.
In still another embodiment of the invention, the semiconductor memory device includes a plurality of terminals for inputting data to and outputting data from the memory block, and the test pattern generation circuit generates a plurality of test patterns in accordance with the address signal received by the test pattern generation circuit, the address signal being received via the plurality of terminals.
In still another embodiment of the invention, the semiconductor memory device includes a plurality of terminals for inputting data to or outputting data from the memory block, and at least one of the plurality of terminals outputs a result by the comparison circuit comparing the test pattern which is read from the memory block against the test pattern which is generated by the test pattern generation circuit.
Thus, according to the present invention, in a test mode for testing a memory block provided on a chip, a test pattern which is generated by a test pattern generation circuit provided on the same chip is written to the memory block via first bus lines having a larger width of the first bus lines than that of second bus lines. Such writing via the first bus lines occurs much faster than writing an externally-supplied test pattern to the memory block via second bus lines.
By recording a plurality of test patterns in a storage section, it becomes possible to output a different test pattern from the test pattern generation circuit depending on an address signal. This makes it possible to subject the memory block to various kinds of tests.
Furthermore, a test pattern which has been generated by a test pattern generation circuit can be once stored in and then read from a memory block. Then, the comparison circuit compares the test pattern which has been read from the memory block against a test pattern which has been generated by the test pattern generation circuit. As a result, it is possible to accurately detect whether a plurality of memory cells included in the memory block are satisfactory or defective.
A plurality of terminals can be utilized both for data input/output to or from the plurality of memory cells of the memory block and for receiving an address signal which is needed by the test pattern generation circuit to generate a test pattern. As a result, the semiconductor memory device can advantageously have a reduced number of terminals as compared to those required in a configuration where terminals for receiving an address signal are separately incorporated in addition to terminals for data input/output.
A plurality of terminals can be utilized for data input/output to or from the memory block, one of which terminals can be further utilized for outputting a comparison result by the comparison circuit. As a result, the semiconductor memory device can advantageously have a reduced number of terminals as compared to those required in a configuration where a terminal for outputting a comparison result by the comparison circuit is separately incorporated in addition to terminals for data input/output.
Thus, the invention described herein makes possible the advantage of, in a test mode for testing a semiconductor memory device, reducing the test mode time while improving the accuracy of the test.
This and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.


REFERENCES:
patent: 5481671 (1996-01-01), Fujisaki
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Mori et al. (A 45ns 64Mb DRAM with a Merged Match-line Test Architecture; IEEE; Mar., 1991).*
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Raghunathan et al. (Test Generation for Cyclic Combinational Circuits; IEEE; Jan. 1994).*
Sen-Chung et al. (LDS-ATPG: An Automatic Test Pattern Generation System for Combinational VLSI Circuits; IEEE; May 1989).*
Kohno et al. (A 14-ns 1-Mbit CMOS SRAM with Variable Bit Organization; IEEE; Oct. 1988).*
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Chih-Chang et al. (Time-Multiplexed Routing Resources for FPGA Design; IEEE; May 1996).*
Self-Test/Connection Technique for Wafer Scale Integration Memory; IBM Technical Disclosure, Bulletin, Sep. 1985, US; NN85091733.*
S. Mori et al., 1991 IEEE ISSCC, pp. 110-111, 1991, “A 45ns 64Mb DRAM with a Merged Match-Line Test Architecture”.

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