Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-01-31

2002-10-01

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S063000, C365S206000

Reexamination Certificate

active

06459639

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority of Japanese Patent Application No. 2000-030912, filed on Feb. 8, 2000, the contents being incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices, in particular, having a function of switching over power supplies to be used, for example, memories such as DRAMs (Dynamic Random Access Memories) including overdrive sense amplifiers.
2. Description of the Related Art
Recently, in a semiconductor memory device represented by a DRAM or the like which enlarges its capacity, a memory device increases its level of integration year after year, and the reduction of an element such as a transistor progresses year after year. Accordingly, a voltage which can be applied to a memory cell part is decreasing year after year from the viewpoints of less energy consumption and reliability.
However, a sense amplifier which amplifies a fine electric charge outputted from a memory cell of the DRAM decreases its driving capacity with the less voltage and hence the time for amplifying a bit line voltage is lengthened. This results in longer cycle time and access time of the DRAM. Therefore, an overdrive type sense amplifier is proposed in order to reduce the voltage which is applied to the memory cell part and to amplify the bit line voltage quickly by the sense amplifier.
FIG. 5A
to
FIG. 5E
are illustrations showing partial structural examples and operations of the overdrive type sense amplifier in general.
FIG. 5A
is a circuit diagram showing one sense amplifier part taken from the sense amplifiers which are provided corresponding to memory cell arrays which are in a matrix state and comprise the DRAM.
As shown in
FIG. 5A
, the sense amplifier is connected to a bit line pair BL and /BL in a flip-flop structure. The drain of a transistor which comprises a not-shown memory cell is further connected to the bit line pair BL and /BL. The sense amplifier amplifies a differential voltage which occurs in the bit line pair BL and /BL according to an electric charge accumulated in a capacitance element of the memory cell which is accessed in reading-out of data.
At this time, the sense amplifier is activated by a signal lex which is supplied from a signal line connected commonly to high potential side terminals of the flip-flops and a signal lez which is supplied from a signal line connected commonly to low potential side terminals of the flip-flops. Namely, as shown in FIG.
5
B and
FIG. 5C
, the signal lex changes to the low level while the signal lez changes to the high level, and the sense amplifier begins to be activated when these reach a certain level.
As shown in
FIG. 5B
, in driving the sense amplifier of the overdrive type sense amplifier, an external voltage (peripheral voltage) Vdd which has a higher level than an internal step-down voltage (core voltage) Viic as a voltage accumulated in the memory is supplied first as a power supply voltage Viid. Then, after a transitional overdrive time tovd, the power supply voltage Viid to be supplied is decreased to the internal step-down voltage Viic which is in the level of the voltage accumulated in the memory.
The change of its voltage levels of the bit line pair BL and /BL is shown in FIG.
5
C. As shown in
FIG. 5C
, the voltage levels of the bit line pair BL and /BL become sharply disparate, and the bit line voltage is amplified in a short time. Thus, the bit line pair BL and /BL are driven in an early step of the drive by using the external voltage Vdd which has the higher level than the internal step-down voltage Viic, which makes it possible to shorten the time for amplifying the bit lines.
Incidentally, in an appropriate situation as shown in
FIG. 5C
, the voltage of the bit line pair BL and/BL is precharged to the voltage of the one-half level of the internal step-down voltage Viic after the amplification.
The overdrive time tovd is decided by a method of a fixed delay element according to a value obtained by a simulation or the like in designing the memory, and by a method of sensing its situation by separately providing a dummy sense amplifier for monitoring. (An application in relation to the latter method has been already filed with the Japanese Patent Office in the name of the present applicant.) In each of the methods, it is not the case that the overdrive time tovd is decided by sensing an electric charge of the actual bit line itself.
Moreover, there arises a need for a quick random access of the DRAM in recent years so that an FCRAM (Fast Cycle RAM) is developed as an example of the device for satisfying the need. The basic technology of this FCRAM is disclosed in WO 98/56004. The FCRAM, one memory block of which is further divided into sub-blocks, is a device which processes a narrower operation area of the sense amplifier by activating the sub-block which is selected by a row address only in the reading-out/writing-in of data, and precharges automatically when the processing completes.
FIG. 6
is a diagram showing a structural example when the overdrive type sense amplifier is applied to the FCRAM, which shows one memory block (bank).
In
FIG. 6
, a row decoder
1
decodes a row address signal and activates a word line to which the memory cell to be accessed is connected among the word lines (not shown) provided on each of the rows of the respective memory cell arrays (sub-blocks)
3
which are arranged in a matrix state.
A column decoder
2
decodes a column address signal, selects the bit line pair to which the memory cell to be accessed is connected among the bit line pair (not shown) provided on each of the columns of the respective memory cell arrays (sub-blocks)
3
which are arranged in a matrix state, and connects the selected bit line pair to a not-shown data-bus.
The sense amplifiers
4
amplify the differential voltage which occurs in the bit line pair according to the electric charge accumulated in the capacitance elements of the memory cells which are accessed in reading-out of data. The sense amplifiers
4
are arranged on each side of the memory cell arrays (sub-blocks)
3
which are arranged in a matrix state in one bank. Power supply wirings for the sense amplifiers (Viid)
5
are the wirings for supplying the power supply voltage to the respective sense amplifiers
4
, which are connected in a mesh state to the memory cell arrays (sub-blocks)
3
and the sense amplifiers
4
which are arranged in a matrix state.
Power supply circuits PS
1
to PS
4
which supply overdrive power supplies are dispersed corresponding to the memory blocks, each of which includes pMOS (pchannel MOS) transistors
6
-1
to
6
-4
,
7
-1
to
7
-4
for switching the power supplies. One pMOS transistors
6
-1
to
6
-4
are connected between the power supply wirings for the sense amplifiers (Viid)
5
and the power supplies of the external voltage Vdd, while the other pMOS transistors
7
-1
to
7
-4
are connected between the power supply wirings for the sense amplifiers (Viid)
5
and the power supplies of the internal step-down voltage Viic. These pMOS transistors
6
-1
to
6
-4
,
7
-1
to
7
-4
comprise a drive circuit of the sense amplifier
4
.
A Viid control circuit
8
controls the turning on/off of the pMOS transistors
6
-1
to
6
-4
,
7
-1
to
7
-4
provided in each of the power supply circuits PS
1
to PS
4
. When driving the sense amplifier
4
by turning on/off the pMOS transistors
6
-1
to
6
-4
,
7
-1
to
7
-4
, this Viid control circuit
8
supplies the external voltage Vdd which has the higher level than the internal step-down voltage Viic to the power supply wirings for the sense amplifiers (Viid)
5
by first turning on the pMOS transistors
6
-1
to
6
-4
on one hand concurrently.
Then, after a transitional overdrive time tovd, the pMOS transistors
6
-1
to
6
-4
on one hand are turned off and the pMOS transistors
7
-1
to
7
-4
on the other hand are turned on concurrently, whereby the internal step-down voltage Viic is

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