Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-04-29

2002-10-08

Tu, Christine T. (Department: 2784)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S718000

Reexamination Certificate

active

06463558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having both a Random Access Memory part and a Logic part therein.
This application is a counterpart of Japanese patent applications, Serial Number 240553/1998, filed Aug. 26, 1998, the subject matter of which is incorporated herein by reference.
2. Description of the Related Art
A Dynamic Random Access Memory (hereinafter DRAM), which is operated in response to a control signal, needs a controller which outputs the control signal to DRAM and a control circuit (hereinafter LOGIC part) comprised of a Micro Processor Unit (MPU) for controlling the controller. A semiconductor device having both a DRAM and the LOGIC part is called an LRAM.
FIG. 6
is a block diagram showing a conventional LRAM. The conventional LRAM will be explained hereinafter with reference to FIG.
6
.
LRAM
300
is made up of the LOGIC part
310
which serves as a control circuit and a RAM part
320
which functions as a memory. The RAM part
320
is controlled by a clock signal CLK and an address signal ADD which are output from the LOGIC part
310
. The RAM part
320
directly outputs an output data us signal DOUT to the LOGIC part
310
. The RAM part
320
also directly receives an input data signal DIN from the LOGIC part
310
.
The LOGIC part
310
is mainly made up of MPU
311
, a memory part
312
which is comprised of Read Only Memory (ROM) or Static Random Access Memory (SRAM) or the like, and a controller
313
for controlling the RAM part
320
.
The MPU
311
, which is controlled by a LOGIC part control signal CTR, controls data reading/writing from and to the memory part
312
and also controls the controller
313
. Furthermore, the controller
313
outputs the clock signal CLK the address signal ADD and the data input signal DIN to the RAM part
320
.
The RAM part
320
includes a timing generator
321
which receives the clock signal CLK, a row/column address buffer
322
which receives the address signal ADD, an input/output buffer
323
which receives the input data signal DIN, and a memory cell array
324
. The RAM part
320
further includes a row decoder
325
which decodes the address signal ADD and outputs a row address signal to the memory cell array
324
, a column decoder
326
which decodes the address signal ADD and outputs a column address signal to the memory cell array
324
, and a sense amplifier
327
. The output data signal DOUT is output from the input/output buffer
323
to the controller
313
in the LOGIC part
310
.
In the conventional LRAM
300
, using the LOGIC part
310
is the only way to access to the RAM part
320
. Accordingly, a test circuit or the like for testing the RAM part
320
must be included in the LOGIC part
310
in order to test the RAM part
320
.
Furthermore, since the RAM part
320
is initialized under the control of the LOGIC part
310
, an operation time of the LRAM
300
becomes long.
Consequently, there has been a need for an improved semiconductor memory device.
SUMMARY OF THE INVENTION
It is an object of the present invention is to provide a semiconductor memory device that may easily input a test pattern from an external device.
It is another object of the present invention is to provide a semiconductor memory device that may initialize a RAM part rapidly.
It is another object of the present invention is to provide a semiconductor memory device that may directly test only a RAM part.
It is another object of the present invention is to provide a semiconductor memory device that may directly read/write an initial data to a RAM part.
According to one aspect of the present invention, for achieving one or more of the above objects, there is provided a semiconductor memory device for receiving an external data from an external device. The semiconductor memory device includes a memory circuit which stores data, a control circuit which outputs a data and a control signal to control the memory circuit and which receives a data stored in the memory circuit, and a selector circuit which selectively transfers either one of the data output from the control circuit or the data from the external circuit to the memory circuit in response to a selection signal. The memory circuit, the control circuit, and the selector circuit in the semiconductor memory device are formed on a single chip.
The above and further objects and novel features of the invention will more fully appear from the following detailed description, appended claims and the accompanying drawings.


REFERENCES:
patent: 4835774 (1989-05-01), Ooshima et al.
patent: 5483493 (1996-01-01), Shin
patent: 5491697 (1996-02-01), Tremel et al.
patent: 5673270 (1997-09-01), Tsujimoto

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