Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2001-04-03

2002-02-12

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S051000, C365S154000

Reexamination Certificate

active

06347062

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device. More particularly this invention relates to a layout of a multi-port SRAM (Static Random Access Memory) cell having CMOS construction.
BACKGROUND OF THE INVENTION
In recent years, there has been an increasing demand for a high-speed processing of electronic devices along with a reduction in weigh and sizes of these devices. The mounting of microcomputers on these electronic devices is now unavoidable. It is also essential to install large-capacity and high-speed processing memories on these microcomputers. Further, along with a rapid distribution of high-performance personal computers, there has also been an increasing demand for large-capacity cache memories. In other words, RAMs that are used by the CPU to execute control programs are required to have a large capacity with high-speed processing.
DRAM (Dynamic RAM) and SRAM are generally used as a RAM. Particularly, SRAM is generally used for cache memories and the like that require high-speed processing. The SRAM is known to have a high-resistance load type memory cell and a CMOS type memory cell. The high-resistance load type is constructed of four transistors and two high-resistance elements. The CMOS type is constructed of six transistors. Because of very small leakage current during data holding, the CMOS type SRAM has high reliability and is used as the main kind of SRAM at present.
Generally, a reduction in the area of the memory cell means not only a reduction in the size of the memory cell array but also a realization of high-speed processing. In order to achieve a higher-speed operation of the SRAM than in the past, various layout proposals have been made so far.
For example, according to the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110, P-well areas and N-well area formed with inverters that constitute a memory cell are disposed so that their boundary lines are parallel with bit lines. Based on this arrangement, diffusion areas within the P-well areas and the N-well area and a cross-connected portion of two inverters are formed in simple shapes respectively having no bending. As a result, the cell area is reduced.
FIG.
21
and
FIG. 22
are layout diagrams of the semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110.
FIG. 21
shows diffusion areas formed on the surface of a semiconductor substrate, a polycrystalline silicon film formed on the diffusion areas, and a ground including a first metal-wiring layer.
FIG. 22
shows an upper ground including second and third metal-wiring layers formed on the upper layer.
As shown in
FIG. 21
, in the center of the memory cell, there is disposed the N-well area in which P-channel type MOS transistors P
101
and P
102
are formed. On both sides of this N-well area, there are formed P-well areas in which N-channel type MOS transistors N
101
and N
103
, and N
102
and N
104
are formed respectively.
The P-channel type MOS transistors P
101
and P
102
and the N-channel type MOS transistors N
101
and N
102
are mutually cross connected to form a CMOS inverter, that is, a flip-flop circuit. The N-channel type MOS transistors N
103
and N
104
correspond to an access gate (a transfer gate).
As shown in
FIG. 22
, bit lines BL and /BL are separately formed as second metal-wiring layers. The bit lines BL and /BL are connected to one end of semiconductor terminals of the lower-layer access gate MOS transistors N
103
and N
104
respectively. A power source line Vdd is formed as a second metal-wiring layer in the center between the bit lines BL and /BL in parallel with these bit lines. The power source line Vdd is connected to one of semiconductor terminals of the lower-layer P-channel type MOS transistors P
101
and P
102
. A word line WL is formed as a third metal-wiring layer in a direction orthogonal with the bit lines BL and /BL. The word line WL is connected to gates of the lower-layer N-channel type MOS transistor N
103
and N
104
. Two ground lines GND are formed as third metal-wiring layers on both sides of the word line WL in parallel with this word line.
As a result of forming the memory cell in this layout, an N-type diffusion area within the P-well area in which the MOS transistors N
103
and N
103
are located and an N-type diffusion area in which the MOS transistors N
102
and N
104
are located can be linear and parallel to the bit lines BL and /BL. This construction can prevent occupation of an unnecessary area.
The length of the cell in a lateral direction, that is, the length of the word line WL, is larger than the length of the cell in a longitudinal direction, that is, the length of the bit lines BL and /BL. Therefore, it becomes easy to provide a layout of a sense amplifier connected to the bit lines BL and /BL. At the same time, the number of cells to be connected to one word line can be reduced. As a result, it is possible to reduce a cell current that flows during the reading. In other words, it is possible to reduce power consumption.
The above-described SRAM memory cell is an example of what is called one-port SRAM. In recent years, there has been introduced a multi-processor technique for achieving high-speed processing of computers. Based on this technique, a plurality of CPUs are required to share one memory area. In this aspect, various layouts have been proposed for a multi-port SRAM that makes it possible to have access to CPUs from two ports to the one memory cell.
For example, according to the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089, a multi-port SRAM construction is realized by disposing a second port in symmetry with a first port on the same layer and by having the two ports formed at the same time.
FIG. 23
shows the layout of the memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089.
As shown in
FIG. 23
, P-channel type MOS transistors P
201
and P
202
and N-channel type MOS transistors N
201
′, N
202
′, N
201
″ and N
202
″ are mutually cross connected to form a CMOS inverter, that is, a flip-flop. N-channel type MOS transistors NA, NB, NA
2
and NB
2
correspond to access gates (transfer gates).
In other words, N-channel type MOS transistors NA and NB make it possible to have an access from one gate via a word line WL
1
, and N-channel type MOS transistors NA
2
and NB
2
make it possible to have an access from the other gate via a word line WL
2
.
Conventional memory cells have a disadvantage that the amount of wiring of the bit lines is large and a delay increases, as the memory cell has a larger length in the direction of the bit lines. The semiconductor memory device disclosed in Japanese Patent Application Laid-Open (JP-A) No. 10-178110 solves this problem for one-port SRAM.
However, this semiconductor memory device does not solve the above problem for a multi-port SRAM generally having two sets of access gates and a drive-type MOS transistor. The memory cell disclosed in Japanese Patent Application Laid-Open (JP-A) No. 07-7089 shows a layout of a multi-port SRAM cell. However, this provides the layout for making it easy to add a second port without generating a large change in the layout of the one-port SRAM cell. This layout does not reduce the size of the multi-port SRAM cell in the direction of the bit lines.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor memory device having a memory cell with a short length in the direction of bit lines, in the construction of a P-well area formed with a pair of CMOS inverters and a N-well area that constitute a multi-port SRAM cell. In the semiconductor memory device of the present invention, the P-well area is divided into two P-well areas. The two P-well areas are disposed on the two sides of the N-well area. The boundaries between P and N-well areas are parallel to the bit lines, and a pair of access gates are formed in each of the two P-well areas.
In the semiconduc

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