Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-12-04

2002-05-07

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

Reexamination Certificate

active

06385095

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as DRAM (Dynamic Random Access Memory), and in particular to a semiconductor memory device compatible with the data of a plurality of types of bit configuration, such as ×16 bit (16 bit width) configuration, ×8 bit (8 bit width) configuration and ×4 bit (4 bit width) configuration.
2. Description of the Related Art
Conventionally, large capacity semiconductor memory devices as represented by DRAM are constructed to be compatible with multiple types of data from varying bit configurations, such as ×16 bit configurations, ×8 bit configurations and ×4 bit configurations by adaptation during the manufacturing process, in order to meet the needs of a variety of users.
However, despite the large increase in the capacity of semiconductor memory devices due to improvements in refined manufacturing technology, some users may demand semiconductor memory devices with even larger memory capacity. For example, the currently most common 256 megabit DRAM is compatible with three types of bit configuration, ×16 bit configuration, ×8 bit configuration and ×4 bit configuration. However depending on the user, there may be a situation where for example 512 megabits memory capacity is needed in an ×4 bit configuration.
In order to satisfy the needs of this kind of user, it would be satisfactory to develop a new semiconductor memory device that has more memory capacity, but developing a new semiconductor memory device requires time, and these needs cannot be satisfied quickly.
As an alternative technology until a new semiconductor memory device is developed, for example, a method has been proposed where a conventional semiconductor memory device which is compatible with data of an ×2 bit (2 bit width) configuration in addition to the aforementioned three types of bit configuration is constructed, and two of these semiconductor memory devices are then used to realize the appearance of an ×4 bit configuration semiconductor memory device of increased capacity.
FIG. 7
shows a sample construction of a data write system of a semiconductor memory device that in addition to the aforementioned three types of bit configuration, namely ×16 bit configuration, ×8 bit configuration and ×4 bit configuration, is also compatible with ×2 bit configuration. The semiconductor memory device shown in this diagram includes data input circuits (DIN in the figure)
700
-
715
for inputting 16 bit data DQ
0
-DQ
15
from an external source, and data write circuits (WAMP in the figure)
800
-
815
for writing the data input by the data input circuits to a memory cell array
900
.
The data output from the data input circuit
700
is distributed to eight data write circuits
800
-
803
and
812
-
815
. The data output from the data input circuit
701
is distributed only to the data write circuit
801
, the data output from the data input circuit
702
is distributed to two data write circuits
802
,
803
, and the data output from the data input circuit
703
is distributed only to the data write circuit
803
. The data output from the data input circuit
715
is distributed to four data write circuits
812
-
815
, the data output from the data input circuit
714
is distributed only to the data write circuit
814
, the data output from the data input circuit
713
is distributed to two data write circuits
812
,
813
, and the data output from the data input circuit
712
is distributed only to the data write circuit
812
.
Similarly, the data output from the data input circuit
704
is distributed to eight data write circuits
804
-
811
, the data output from the data input circuit
705
is distributed only to the data write circuit
805
, the data output from the data input circuit
706
is distributed to two data write circuits
806
and
807
, and the data output from the data input circuit
707
is distributed only to the data write circuit
807
. The data output from the data input circuit
711
is distributed to four data write circuits
808
-
811
, the data output from the data input circuit
710
is distributed only to the data write circuit
810
, the data output from the data input circuit
709
is distributed to two data write circuits
808
,
809
, and the data output from the data input circuit
708
is distributed only to the data write circuit
808
.
Of the sixteen data write circuits
800
-
815
, a mask signal LWM for masking the writing of the lower 8 bits of the 16 bit data DQ
0
-DQ
15
which is input from an external source, is input into the data write circuits
800
-
807
. A mask signal UWM for masking the writing of the upper 8 bits of the 16 bit data DQ
0
-DQ
15
, is input into the data write circuits
808
-
815
.
FIG. 8
shows the structure of a mask signal generation circuit
850
for generating the upper bit range mask signal UWM and the lower bit range mask signal LWM.
In
FIG. 8
, a mask control signal UDQM for the upper 8 bits, which is received from an external source, is received by an input circuit
851
and is then output via a buffer consisting of inverters
852
and
853
to the data write circuits
808
-
815
shown in
FIG. 7
as the mask signal UWM. Furthermore, a mask control signal LDQM for the lower 8 bits, which is received from an external source, is received by an input circuit
854
and is then output via a buffer consisting of inverters
855
and
856
to the data write circuits
800
-
807
shown in
FIG. 7
as the mask signal LWM.
In this example, in the handling of 16 bit data, the mask signal UWM and the mask signal LWM are activated complementarily, and the data write circuits
800
-
807
and the data write circuits
808
-
915
are controlled complementarily. Consequently, of the 16 bit data DQ
0
-DQ
15
, the writing of the lower 8 bit range data DQ
0
-DQ
7
and the upper 8 bit range data DQ
8
-DQ
15
are respectively masked. Furthermore, in the handling of 2 bit data, 4 bit data, and 8 bit data, then as shown in the construction of
FIG. 8
, as a result of the formation of a signal path PJ from the input circuit
851
to the input circuit
854
, the mask signal UWM and the mask signal LWM become equivalent, and only the mask control signal UDQM, which is received from an external source, is valid. In this case, for data from each of an ×2 bit configuration, an ×4 bit configuration and an ×8 bit configuration, the mask control signal UDQM controls whether or not the writing of all bits will be masked.
In
FIG. 7
, the memory cell array
900
incorporates an address signal map which is used according to the bit configuration of the data to be stored. In this example, when 16 bit data is to be stored, none of address signals Y
9
, Y
11
, Y
12
are used, and the 16 bit data output from the data write circuits
800
-
815
is written directly to the memory cell array
900
. Furthermore, when 8 bit data is stored, either the data write circuits
801
,
803
,
805
,
807
,
808
,
810
,
812
,
814
, or the data write circuits
800
,
802
,
804
,
806
,
809
,
811
,
813
,
815
are selected by the address signal Y
9
. In this case, the address signals Y
11
, Y
12
are not used.
In addition, when 4 bit data is stored, either the data write circuits
802
,
803
,
806
,
807
,
808
,
809
,
812
,
813
or the data write circuits
800
,
801
,
804
,
805
,
810
,
811
,
814
,
815
are selected according to the address signal Y
11
, and one quarter of the totality of data write circuits are selected by the address signals Y
9
and Y
11
. In this case the address signal Y
12
is not used. Furthermore, when 2 bit data is stored, either the data write circuits
800
-
807
or the data write circuits
808
-
815
are selected according to the address signal Y
12
, and one eighth of the totality of data write circuits are selected according to the address signals Y
9
, Y
11
and Y
12
.
Although not shown in the figure, the data output from the data write

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