Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-04-14

2002-07-09

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000

Reexamination Certificate

active

06418073

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device for improving the precharge speed of a bit line in a precharge circuit in order to accelerate the reading and writing of data.
2. Description of the Related Art
In a semiconductor memory device such as a DRAM (dynamic random access memory), a precharge operation is carried out on the bit line pair connected to a sense amplifier at a timing cycle prior to the reading and writing of data. By accelerating the operation of this precharge, the read/write processing of data to the memory cell can be accelerated.
FIG. 9
shows an example of the essential components of a circuit from the memory cell to the sense amplifier in a conventional DRAM.
In
FIG. 9
, the circuit that precharges each of the bit lines (BLT
1
-BLTn, BLN
1
-BLNn) of bit line pair BL
1
to bit line pair BLn has the structure shown in
FIG. 9
, and specifically is structured by precharge drive circuit
1001
to precharge drive circuit
100
q
(q being a natural number), and precharge circuit SW
1
to precharge circuit SWn. Respective memory cell MS
1
to memory cell MSm (m being a natural number, and 2×n=m), for example, are connected to each of the bit lines (BLT
1
-BLTn, BLN
1
-BLNn) of bit line pair BL
1
to bit line pair BLn.
When the data of memory cell MS
1
is read, for example, the reading operation is carried according to the timing chart in FIG.
10
. At this time, because the control signal PDLB
1
is at L level, each of the bit lines of bit line pair BL
1
to bit line pair BLn is precharged by precharge circuit SW
1
to precharge circuit SWn.
First, at time t
1
, when a specified RAS address that indicates memory cell MS
1
is input, the internal address signal output from the row address decoder circuit (not illustrated) is output, and the control signal RASB supplied externally inverts from H level to L level. Thereby, based on the input control signal RASB, at time t
2
the sense amplifier selection circuit
1
outputs a control signal PDLB
1
at H level to precharge drive circuit
1001
to precharge drive circuit
100
q
provided on the sense amplifier row associated with the specified address decoder.
In addition, at time
3
, precharge drive circuit
1001
to precharge drive circuit
100
q
inverts each of the control signals PDL
1
from H level to L level. Thereby, the charge operation of each of the bit lines of bit line pair BL
1
to bit line pair BLn is completed. At this time, each of the bit lines of bit line pair BL
1
to bit line pair BLn is charged, for example, to the value of Vcc/2 with respect to the power supply voltage Vcc of the memory.
Thereby, the MOS transistor that carries out the equalization of bit line pair BL
1
to bit line pair BLn in precharge circuit SW
1
to precharge circuit SWn is turned OFF, and the MOS transistor for the precharge power supply is turned OFF.
Additionally, at time t
4
, each of the bit lines of bit line pair BL
1
to bit line air BLn becomes OPEN, and the inverts from L level to H level by the activation of the wordline SWL
0
.
As a result, when the data of H level is recorded in the memory cell MS
1
, the charge stored in the capacitor of the memory cell MS
1
is supplied to the bit line BLT
1
, the voltage of bit line BLT
1
rises above the precharge voltage “Vcc/2”, and bit line BLN
1
remains at precharge voltage “Vcc/2” to act as a dummy line.
Additionally, at time t
5
, an internal address signal is output from a column decoder (not illustrated) based on the column address supplied externally. Thereby, specified sense amplifier SA
1
, sense amplifier SA
2
, sense amplifier SAk (k being a natural number, and n>k) are activated. That is, bit line BLT
1
and bit line BLN
1
are connected to the sense line in the sense amplifier SA
1
, bit line BLT
2
and bit line BLN
2
are connected to the sense line in the sense amplifier SA
2
, . . . , and bit line BLTk and bit line BLNk are connected to the sense line in the sense amplifier SAk.
Thereby, the sense amplifier SA
1
increases the voltage difference between bit line BLT
1
and bit line BLN
1
, and H level data is output to the output drive via a column switch (not illustrated) and a data amplifier (not illustrated).
Additionally, at timing t
6
, the control signal RASB output from a row address decoder circuit (not illustrated) inverts from L level to H level. Thereby, at time t
7
, sense amplifier SA
1
, . . . , sense amplifier SAk are inactivated, wordline SWL
10
is similarly deactivated, and H level inverts to L level. Thereby, each of the bit lines of bit line pair BL
1
to bit line pair BLn becomes OPEN.
Additionally, at time t
8
, control signal RASB inverts to H level, and thereby the sense amplifier selection circuit
1
inverts the control signal PDLB
1
from H level to L level.
As a result, at time t
9
, precharge drive circuit
1001
to precharge drive circuit
100
q
invert each control signal PDL
1
from L level to H level. Thereby, the MOS transistors in precharge circuit SW
1
to precharge circuit SWn are turned ON, and thus each of the bit lines of bit line pair BL
1
to bit line pair BLn is precharged. In addition, at time t
15
, the voltages of each of the bit lines of bit line pair BL
1
to bit line pair BLn become Vcc/2, and the precharge is completed.
By shortening the time of the charge from time t
8
to time t
15
, the waiting time up to the reading of the data is shortened, and the read operation can be carried out rapidly. Reducing the time to turn ON the MOS transistors in precharge circuit SW
1
to precharge circuit SWn and increasing the charge current of the MOS transistors in precharge circuit SWi to precharge circuit SWn are methods that can be considered for achieving this objective.
According to this method, the channel length of the MOS transistors in the precharge circuit SW
1
to precharge circuit SWn is determined by such factors as voltage, and thus enlarging the transistor width of the MOS transistors in the precharge circuit SW
1
to precharge circuit SWn or increasing the channel conductance (conductance) of these MOS transistors in the ON state can be considered.
However, because the channel width of the MOS transistors used would be enlarged, the surface area of the formation region of precharge circuit SW
1
to precharge circuit SWn would increase. If this is done, since precharge circuit SW
1
to precharge circuit SWn are formed in regions SA provided by the sense amplifier circuits, etc., shown in
FIG. 11
, the result is widening the boundary portion of the limited memory cell region MS, and thus the total chip area of the semiconductor memory device is increased. Here,
FIG. 11
is a concept drawing showing the structure of a DRAM using a shared sense method.
Therefore, rather than enlarging the channel width of the MOS transistors that form precharge circuit SW
1
to precharge circuit SWn, increasing the drive capability of the MOS transistors forming precharge circuit SW
1
to precharge circuit SWn by decreasing the rise time of the electrical potential of the gates of these MOS transistors, that is, either by accelerating the timing of the precharge start by decreasing the turn-on time of these MOS transistors, or by increasing the channel conductance by increasing the gate voltage of these MOS transistors, can be considered.
However, in the above-described semiconductor memory device, the MOS transistors of precharge drive circuit
1001
to precharge drive circuit
100
q
that conduct the charge current for driving the MOS transistors forming precharge circuit SW
1
to precharge circuit SWn, which is to say, apply the charge to the gates of these MOS transistors, are formed by p-channel type MOS transistors PM.
In addition, precharge drive circuit
1001
to precharge drive circuit
100
q
are each formed on the associated cross areas CR (refer to FIG.
11
). Thus, when increasing the channel width of the MOS transistor PS in attempting to reduce the turn-on time of the MOS transistors that form precharge circuit SW

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