Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator

Reexamination Certificate

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Details

C365S230030, C365S203000, C365S207000, C365S189070, C365S210100

Reexamination Certificate

active

08009488

ABSTRACT:
A semiconductor memory device includes a plurality of memory cell array blocks connected to word lines, source lines, and bit lines, each memory cell array including memory cells each having a transistor with a floating body, a reference voltage generator configured to have a reference memory cell and generate a reference voltage for bit line sensing corresponding to a current flowing into a reference memory cell during a data read operation, first and second prechargers configured to precharge a bit line connected to non-selected memory cells to the reference voltage in response to first and second precharge control signals during the data read operation, and a sense amplifier configured to sense and amplify a voltage difference between a bit line connected to the selected memory cells and a bit line connected to the non-selected memory cells during the data read operation.

REFERENCES:
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patent: 7027334 (2006-04-01), Ikehashi et al.
patent: 7511982 (2009-03-01), Kurjanowicz et al.
patent: 2007/0025146 (2007-02-01), Huang
patent: 2007/0189068 (2007-08-01), Lee
patent: 2007/0189094 (2007-08-01), Ohsawa
patent: 2008/0170444 (2008-07-01), Hoenigschmid
patent: 11-213664 (1999-08-01), None
patent: 2004-335883 (2004-11-01), None
patent: 10-2004-0096781 (2004-11-01), None
patent: 10-0675299 (2007-01-01), None

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