Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2011-08-30

2011-08-30

Phan, Trong (Department: 2827)

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

C365S189080, C365S189170, C365S230060

Reexamination Certificate

active

08009485

ABSTRACT:
A semiconductor memory device includes training drivers configured to transmit one of data and a predetermined training data pattern from a first data lines to a second data lines in response to a training control signal which is produced by decoding a read training command; and the second data lines configured to transmit an output of the training drivers. The semiconductor memory device according to the present invention can exactly measure a delay time, which is changed according to the surrounding environments between a semiconductor memory device and a data processing unit, through a data training and operation timing can be also adjusted based on the measured delay time.

REFERENCES:
patent: 7692982 (2010-04-01), Yoon
patent: 2008/0225603 (2008-09-01), Hein
patent: 100557221 (2006-02-01), None
patent: 10-2006-0026661 (2006-03-01), None
“Qimonda GDDR5-Whitepaper”, Aug. 2007, 10 pages.

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