Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-09-29

2001-03-06

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S207000, C365S233100

Reexamination Certificate

active

06198679

ABSTRACT:

FIELD OF THE INVENTION
The present invention pertains to a semiconductor memory device. In particular, the present invention pertains to dynamic RAM (DRAM) that reads and writes data in synchronization with an external clock signal.
BACKGROUND OF TEE INVENTION
In recent years, there has been a demand on reading and writing data at a high speed from and into semiconductor memory devices, such as dynamic RAM. Synchronous dynamic RAM that can read and write data in synchronization with an external clock signal has been developed to meet the aforementioned demand. In such synchronous dynamic RAM, a command is input based on a logical combination of signals, such as CS (chip select), RAS (row address strobe), CAS (column address strobe), WE (write enable), etc. In an operation mode corresponding to the command, data are read or written in synchronization with an external clock signal.
As described above, a synchronous dynamic RAM reads and writes data in synchronization with an external clock. As the frequency of the clock signal increases, e.g. to 125 MHz, 133 MHz, or 143 MHz, the operating speed of the internal circuit of the synchronous dynamic RAM must also increase in step with this increase in clock frequency. For example, when the frequency of the external clock signal is 125 MHz, data must be read or written consecutively every 8 ns (nanosecond) in burst mode. When the frequency of the external clock signal is 133 MHz data must be read or written consecutively every 7.5 ns in burst mode. When the frequency of the external clock is 143 MHz, data must be read or written consecutively every 7 ns in burst mode.
The objective of the present invention is to provide a semiconductor memory device that can read and write data at a high speed.
SUMMARY OF THE INVENTION
In order to realize the aforementioned purpose, the present invention provides a semiconductor memory device characterized by the following facts: the semiconductor memory device has a memory array composed of plural memory cells arranged at the positions where plural bit line pairs cross plural word lines, plural sense amplifiers that are electrically connected to the aforementioned plural bit line pairs, respectively, and are used to determine the potential difference between the aforementioned bit line pairs, input/output line pairs that are used to transfer the data read from the aforementioned memory cells and the data to be written into the memory cells, plural first switch circuits that electrically connect the aforementioned plural sense amplifiers to the aforementioned input/output line pairs, respectively, a timing control signal generating circuit that is used to generate a timing control signal, a row decoder circuit that activates one of the aforementioned plural word lines corresponding to a row address signal, and a column decoder circuit that provides a column select signal used to activate a desired first switch circuit from the aforementioned plural first switch circuits corresponding to the aforementioned timing control signal and a column address signal; during a data write operation, the pulse width of the aforementioned timing control signal is set so that it is shorter than the pulse width of the timing control signal during a data read operation; during a data write operation, the width of the pulse used to activate the aforementioned column select signal is shorter than the width of the pulse used to activate the column select signal during a data read operation.
In the present invention, the pulse width of the timing control signal (FY signal) that determines the pulse width of the column select signal (YS signal) is different during a data read operation than during a data write operation. During a data read operation, the width of the pulse used to activate the column select signal is enlarged. The time needed for the bit line pair to be connected to the input/output line pair and for the sense amplifier to determine the potential difference is prolonged so that a sufficient potential difference appears at the input/output line pair. During a data write operation, the width of the pulse used to activate the column select signal is reduced. The time needed for initializing the input/output line pair, that is, the precharge time, is prolonged so that the input/output line pair can be completely initialized. Consequently, data can be read correctly during both a write and read operation synchronized with a high-speed clock signal.


REFERENCES:
patent: 6058044 (2000-05-01), Sugiura

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