Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-01-25

2001-05-15

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S201000

Reexamination Certificate

active

06233187

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices, and more particularly to semiconductor memory devices that include an array of memory cells that each include a transistor and a capacitor.
BACKGROUND OF THE INVENTION
FIG. 7
shows a circuit diagram of a conventional semiconductor memory device, designated by the general reference character
700
. The semiconductor memory device
700
is shown to include a “half source voltage” (HVCC) signal generator
701
, memory cells (MCil to MCin), precharge circuits (PC
1
to PCn), digit lines (D
1
/#D
1
to Dn/#Dn), and sense amplifiers (SA
1
to SAn). The HVCC signal generator
701
can supply a voltage that is ½ VCC, where VCC is a power source voltage. In the reference characters for memory cells (MCi
1
to MCin), the value “i” can be a positive integer that can correspond to a row of an array. Each memory cell (MCi
1
to MCin) can include a transistor Q and a capacitor C. Precharge circuits (PC
1
to PCn) can precharge corresponding digit lines (D
1
/#D
1
to Dn/#Dn) according to a precharge signal BLP. The symbol “#” can indicate that a line can carry a negative logic signal.
In the arrangement of
FIG. 7
, the HVCC signal generator
701
provides a potential at the ½VCC level to a node N
2
and a node N
3
. Node N
2
can provide a precharge level HVCD to the digit lines (D
1
/#D
1
to Dn/#Dn). Node N
3
can provide an “opposite-to-cell” level HVCP
1
to memory cells (MCi
1
to MCin). Within the memory cells (MCi
1
to MCin), each capacitor C can include a data storage terminal connected to its corresponding transistor Q, and an opposing terminal. The opposing terminals can be commonly connected to node N
3
.
The HVCD and HVCP
1
levels are driven to a ½VCC value for a number of reasons. First, precharging the digit lines (D
1
/#D
1
to Dn/#Dn) to such a level can provide for better sense margins when sensing data values stored in the memory cells (MCi
1
to MCin). Second, precharging digit lines (D
1
/#D
1
to Dn/#Dn) and maintaining node
3
at a ½VCC level can serve as a countermeasure against variations in power supply levels (“bumps”). Third, maintaining node
3
at the ½VCC level can protect memory cells against undesirable high voltages across memory cell capacitors. Fourth, precharging the digit lines (D
1
/#D
1
to Dn/#Dn) to a ½VCC level can, for typical data value combinations, reduce digit line precharge current. The first and second reasons can be particularly important in a semiconductor memory device. If the HVCD and HVCP
1
levels vary during operation, unless the values are returned to the ½VCC level immediately, the semiconductor memory device can fail due to a degraded sense margin.
Accordingly, to avoid failures such as those described above, a conventional semiconductor memory device can maintain a precharge potential HVCD and an opposite-to-cell potential HVCP
1
at a ½VCC level. However, in order to carry out certain test modes, an HVCC generating circuit can include a transfer gate within. In such an arrangement, during a test mode, the transfer gate can be turned off. The opposite-to-cell HVCP
1
can then be placed to a low power supply level (such as “ground”) or to a high power supply level (such as VCC).
As noted above, a conventional semiconductor memory device can have an opposite-to-cell potential HVCP
1
that is connected to a precharge potential by a passgate situated within an HVCC generating circuit. In such an arrangement, if there is a potential level fluctuation in a remotely situated memory cell, the precharge potential may not be supplied as the opposite-to-cell potential at a sufficient enough rate. As a result, such a rate of supply may be so low that proper sense margins are not maintained and erroneous operation can result.
More particularly, low logic values can be written into memory cells after power is applied to the device. Coincidentally, the memory cells can be refreshed. In such an operation, the floating data nodes, for example, those data nodes that have not yet had any data written into them, can be driven to a high level (VCC for example). Such a rising potential at data nodes can result in the opposite-to-cell level HVCP
1
also rising in potential. This can lead to a device failure when reading low logic levels from memory cells having such a raised HVCP
1
level.
In even more detail, when power is switched on in a semiconductor memory device, the opposite-to-cell level HVCP
1
can rise to a ½VCC level. Immediately thereafter, when a coincidental refresh operation occurs, the level at floating cell data nodes can be driven toward the VCC level. Such a rise in potential can result in the opposite-to-cell level HVCP
1
also rising, due to capacitive coupling between the high logic values on the previously floating refreshed data nodes and the opposite-to-cell node carrying the HVCP
11
level. If the HVCC level generating circuit
701
has sufficient level supplying activity to compensate for such a rise in the opposite-to-cell level HVCP
1
, normal operations can proceed without failure due to improper sense margins. However, conventional approaches may not be able to compensate for higher than desired opposite-to-cell levels that can lead to failures when reading logic zero values.
For example, a conventional HVCC level generating circuit
701
can be constructed with a transfer gate to accommodate different HVCP
1
levels in a test mode. Due to the transfer gate, in a non-test mode, where the ½VCC level is being supplied as the HVCD and HVCP
1
levels, the HVCC level generating circuit
701
may not be able to meet fluctuations in HVCP
1
levels introduced by a coincidental refresh, as described above.
Further, in a conventional semiconductor memory device, memory cells may be situated remotely from the HVCC level generating circuit
701
. Consequently, due to parasitic resistance and/or capacitance, the HVCC level generating circuit
701
may not be able to meet fluctuations in HVCP
1
levels introduced by a coincidental refresh as previously described.
Thus, in a conventional case, a logic low level can be written into a number of cells prior to a coincidental refresh operation. A coincidental refresh operation may then drive logic high levels into those cells that have not yet had data written into them. This logic high level, due to capacitive coupling, can cause a rise in the opposite-to-cell level HVCP
1
. Then, if data is read from (or refreshed in) those cells storing a logic low, due to the undesirable high HVCP
1
level, sense amplifiers may erroneously detect a high logic level instead of the stored low logic level. This causes a failed read operation.
It would be desirable to arrive at some way of addressing the above-described drawbacks to conventional semiconductor memory devices.
SUMMARY OF THE INVENTION
Embodiments of the present invention can remedy possible erroneous read operations that occur after a coincidental refresh operation. According to an embodiment, a semiconductor memory device can have a half source voltage supply circuit that supplies a half source voltage to memory cells and to precharge circuits. The semiconductor memory device can prevent degradation of sense margins by blocking unwanted fluctuations in memory cell nodes.
According to one embodiment of the present invention, a semiconductor memory device uses a half power source level as an opposite-to-cell potential and a digit line precharge potential. An opposite-to-cell potential can be the potential of a node situated opposite to a data storage node in a memory cell. The semiconductor memory device can further include shunting means that shunt the opposite-to-cell level and the precharge level. Such shunting means can be placed at various locations close to sense amplifier areas and thereby inhibit the development of fluctuations in signals of memory cells, even memory cells that are situated at remote ends of the device. This

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