Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-07-19

2001-07-31

Nelms, David (Department: 2818)

Static information storage and retrieval

Read/write circuit

Signals

C365S201000, C365S230060

Reexamination Certificate

active

06269031

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a semiconductor memory device which generates a column address selecting signal and transfers data within a rise time period of the generated column address selecting signal.
The semiconductor memory device such as the random access memory generates a column address selecting signal on the basis of internal clock frequency, so that within a rise time period of the generated column address selecting signal, a data transfer is made between the semiconductor memory device and a host device such as CPU through a digit line selected by the generated column address selecting signal.
The rise time period of the generated column address selecting signal depends upon a pulse width of the column address selecting signal. The rise time period of the column address selecting signal will hereinafter be referred to as an active width.
In recent years, as the high speed performance of the CPU has been on the improvement, it has been on the requirement for increasing the operating frequency of the semiconductor memory device. If the semiconductor memory device operates depending upon a frequency of a clock signal, then it is possible that an operational margin of the active width of the column address selecting signal is made narrow.
The advanced semiconductor memory device takes another operational system such that the advanced semiconductor memory device operates so that the active width of the column address selecting signal is fixed independent from the frequency of the clock.
If, however, the advanced semiconductor memory device operates so that the active width of the high frequency column address selecting signal is fixed independent from the frequency of the clock, then it is possible in case that all of chips provided internally operate in the active width of the high frequency column address selecting signal, whereby it is possible that chips are defective which have been inoperable in the high frequency column address selecting signal for selection or evaluation on the chips.
In the above circumstances, it had been required to develop a novel semiconductor memory device free from the above problem.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a novel semiconductor memory device free from the above problems.
It is a further object of the present invention to provide a novel semiconductor memory device operable in an appropriate active width of a column address selecting signal without any defective operation of all of internally provided chips.
The present invention provides a semiconductor memory device comprising: a control signal generator circuit for generating a set signal; a delay circuit connected to the control signal generator circuit for receiving the set signal and delaying the set signal with a predetermined delay time to generate a reset signal; a set/reset latch circuit connected to the delay circuit and the control signal generator circuit for receiving the reset signal and the set signal to generate a column address selecting control signal on the basis of the reset signal and the set signal; a column address decoder circuit connected to the set/reset latch circuit for receiving the column address selecting control signal to generate a column address selecting signal with a pulse width depending on the column address selecting control signal; and a memory cell array connected to the column address decoder circuit for receiving the column address selecting signal to execute a data transfer operation within a rise-time period of the column address selecting signal, wherein the delay circuit is capable of varying the delay time of the reset signal.
The above and other objects, features and advantages of the present invention will be apparent from the following descriptions.


REFERENCES:
patent: 6088281 (2000-07-01), Miyakawa et al.

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