Semiconductor integrated circuit having power supply voltage...

Details Semiconductor integrated circuit having power supply voltage... Semiconductor integrated circuit having power supply voltage...

1998-02-26

2001-04-10

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S077000

Reexamination Certificate

active

06215332

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit having a power supply voltage detecting function, and more particularly, a semiconductor integrated circuit, whose circuit functions are all ceased at a power supply voltage of a value or lower, while in part at a power supply voltage of a higher value, but whose circuit functions are all operable at a power supply voltage of a sufficiently further higher value, whereby a wrong operation in a state of a low voltage is prevented from occurring.
In a non-volatile semiconductor memory in which data write and electrical erase can be performed (flash memory EEPROM), its internal operations are controlled in such a manner that a power supply voltage V
DD
is detected, and during a time when a value of the V
DD
is equal to or lower than a first voltage level (V
POWERON
), all the functions of its internal circuits are ceased, while during a time when a value of the V
DD
is higher than the first voltage level (V
POWERON
) but still lower than a second voltage level (V
LVDD
), which is lower than an operation guarantee voltage, a write/erase operation cannot be performed, though a data read operation can be performed. Thereby, wrong write and wrong erase both prevented from occurring.
That is, a flash EEPROM works as a read-only memory when a power supply voltage V
DD
is higher than a V
POWERON
level but lower than a V
LVDD
level, and data in a memory cell is not changed by a write/erase operation therein.
Since an operation is unstable when a power supply voltage V
DD
is higher than the V
POWERON
level, but it is lower than the V
LVDD
level which is a regular operation guarantee voltage level, data write and erase, which entail a change in data in a memory cell, are not performed. This is achieved in such a manner that a level of the power supply voltage V
VDD
is internally detected and a write/erase command from the outside is not accepted, if V
DD
<V
LVDD
. A write/erase operation is ceased when a state of V
DD
>V
LVDD
is given by some influence or other, even after a write/erase operation is started by receiving an external command in a state of V
DD
<V
LVDD
l.
In order to perform the above mentioned control, there are a need for a circuit detecting two voltage levels of the V
POWERON
and the V
LVDD
in a chip.
Since the V
POWERON
level is a voltage level which guarantees a read operation, it is linked with an internal power supply margin. Generally, in the case of a CMOS circuit, the level has more chances to be set at a voltage of the order of the sum of threshold voltages of a p-channel MOS transistor and an n-channel MOS transistor.
FIG. 1A
shows a conventional voltage detection circuit for detecting the V
POWERON
level. The V
POWERON
in the voltage detection circuit is given by V
POWERON
=V
THN
+|V
THP
| (V
THN
and V
THP
are respectively threshold voltages of n and p-channel MOS transistors). In this circuit, a resistor R
31
and a current path between the source and drain of an n-channel MOS transistor (hereinafter referred to as NMOS)
41
are connected in series between nodes of a power supply voltage V
VDD
and the ground potential. The gate of the NMOS
41
is connected to a connection node between an end of the current path and the resistor R
31
. Besides, a current path between the source and drain of an p-channel MOS transistor (hereinafter referred to as PMOS)
42
and a resistor R
32
are in series connected between the nodes of the power supply voltage V
VDD
and the ground potential. The gate of the PMOS
42
is connected to the connection node between the resistor R
31
an end of the current path of the NMOS
41
.
An amplifier circuit
43
is connected to a connection node between an end a current path of the PMOS
42
and the resistor R
32
, wherein the amplifier circuit
43
comprises two inverters having cascade connection and produces a detection signal S
POWERON
showing that a power supply voltage V
DD
is lower or higher than a V
POWERON
through voltage amplification of a signal at the connection node.
In such a constitution, a detection signal S
POWERON
is H level when a power supply voltage V
DD
is lower than a V
POWERON
level (V
THN
+|V
THP
|) and a detection signal level is L level when a power supply voltage V
DD
is higher than the V
POWERON
level (V
THN
+|V
THP
|).
FIG. 1B
shows another circuit constitution of a conventional voltage detection circuit for detecting a V
POWERON
level in a similar manner. This circuit employs a pn junction diode
44
instead of the NMOS
41
of FIG.
1
A and is further different from it in that the V
POWERON
level is given by V
f
+|V
THP
|(V
f
is a voltage drop in a forward direction of a PN junction diode).
Another voltage detection level V
LVDD
of a power supply has more chances to be determined by a power supply circuit in a write or erase operation as a factor.
FIG. 2A
shows a symbolic diagram of a non-volatile transistor with a floating gate and control gate, which is used as a flash EEPROM memory cell and
FIG. 2B
is a table collectively showing voltages supplied to the control gate (VG), drain (VD), source (VS) and back gate (VSUB) in data read/write/erase operations of the non-volatile transistor. As shown in the figure, an operation voltage of the memory cell requires to be higher voltage, positive or negative, (10V, 6V, −7V) for a write/erase operation as compared with a read operation.
In a flash EPROM, these high voltages are internally generated, for example, by use of a booster circuit as shown in FIG.
3
. The booster circuit comprises diodes
51
connected in series, and capacitors
52
and inverters
53
,
54
used for boosting an anode and cathode of each diode
51
alternately with clock signals of different phases.
A value of a boosted voltage V
out
obtained in the booster circuit is strongly dependent on the number of the diodes (N) and a value of a power supply voltage V
DD
and given by the following equation:
V
out
≦N×
(
V
DD
−Vf
)
where Vf is a voltage drop in a diode.
Therefore, the number of necessary steps (N) in a booster circuit is different according to an operation voltage for guarantee.
A relation in magnitude between V
POWERON
and V
LVDD
levels in a integrated circuit of V
DD
=5V has a large difference and for example, the settings are like V
POWERON
=2V and V
LVDD
=3.5V.
FIG. 4
shows an example of a conventional voltage detection circuit for detecting the V
LVDD
level. Two resistors
61
,
62
are in series connected between a node of the power supply voltage V
DD
and the node of the ground voltage. The power supply voltage V
DD
is divided by the two resistors
61
,
62
and supplied to a non-inversion input terminal (+) of an operational amplifier
63
. A reference potential V
ref
is supplied to an inversion input terminal (−) of the operational amplifier
63
and the operational amplifier
63
compares both input potentials in magnitude. A comparison output of the operational amplifier
63
is amplified by an inverter
64
and thereby a detection signal SLV
DD
of H level or L level is generated.
The above mentioned reference voltage V
ref
is a voltage which has no dependence on the V
DD
level and, for example, as shown
FIG. 5
, it is generated in a circuit constituted of diodes
71
,
72
, resistors
73
to
75
and an operational amplifier
76
. The circuit is a generally known BGR (Band Gap Reference) circuit.
Now, when values of the resistors
61
,
62
are respectively indicated by Ra and Rb, the detection signal S
LVDD
output from the voltage detection circuit of
FIG. 4
achieves H level if the following equation is satisfied, which is:
VDD<
{(
Ra+Rb
)/
Rb}V
ref
In the case where an integrated circuit is guaranteed so that it is operable with a power supply voltage of 5V, since such a condition V
LVDD
>>V
POWERON
can be set, it has not been considered that a relation in ma

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