Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

2000-03-15

2001-04-03

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S189110

Reexamination Certificate

active

06212116

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Application No. H11-70758 filed on Mar. 16, 1999 in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device such as a MOS memory, and more particularly, it relates to a static RAM having a load circuit capable of setting bit lines to an intermediate voltage.
2. Related Background Art
FIG. 1
is a circuit diagram around the bit lines of a conventional static random access memory (SRAM). As shown in
FIG. 1
, disposed between two bit lines BLA and BLB are a plurality of memory cells MC
1
, MC
2
to MCn, an initialization circuit
1
for initializing the voltages of these bit lines BLA and BLB, and a load circuit
2
capable of setting the bit lines BLA and BLB to an intermediate voltage so that low level voltage of the bit lines BLA and BLB does not lower excessively. Each of these circuits is constituted of MOS transistors.
The initialization circuit
1
includes an equalizing transistor Q
1
for short-circuiting both the bit lines BLA and BLB during the address transition of memory cells, that is, when carrying out change-over between selection and non-selection of the memory cells, and precharge transistors Q
2
and Q
3
for precharging the bit lines BLA and BLB, respectively. The gate terminals of these transistors Ql to Q
3
are all connected to a signal FI
1
. The voltage level of the signal FI
1
is controlled by an address transition detecting circuit (not shown), set to a high level in a stationary state, and temporarily set to a low level during the address transition. That is, the signal to be supplied to the signal FI
1
is a one shot pulse signal, and the address transition detecting circuit is constituted of a known one shot pulse generating circuit.
The load circuit
2
has load transistors Q
4
and Q
5
for setting the low level voltages of the bit lines BLA and BLB to the intermediate voltage, respectively. The gate terminals of these transistors Q
4
and Q
5
are all connected to a ground terminal, and they are always in an ON state.
The memory cells MC
1
,MC
2
-MCn are constituted of, for example, a known circuit as shown in FIG.
2
.
FIG. 2
shows an example in which the memory cells MC
1
, MC
2
. . . are constituted of two PMOS transistors Q
11
and Q
12
and four NMOS transistors Q
13
to Q
16
. The NMOS transistors Q
13
and Q
14
turn on/off in accordance with logic of a word line WL. The transistors Q
11
and Q
15
are connected in series between a power supply terminal VDD and an ground terminal VSS, and the transistors Q
12
and Q
16
are connected in series between the power supply terminal VDD and the ground terminal VSS. The gate terminals of the transistors Q
1
and Q
15
are connected to the drain terminal of the transistor Q
14
, and the gate terminals of the transistors Q
12
and Q
16
are connected to the drain terminal of the transistor Q
13
.
The memory cells MC
1
and MC
2
of
FIG. 1
are both connected to the bit lines BLA and BLB, the memory cell MC
1
is connected to a word line WL
1
, and the memory cell MC
2
is connected to a word line WL
2
.
FIG. 3A
is a diagram showing the voltage changes of the bit lines BLA and BLB during the address transition,
FIG. 3B
is a diagram showing the voltage change of the signal FI
1
during the address transition, and
FIG. 3C
is a diagram showing the voltage changes of the word lines WL
1
and WL
2
during the address transition.
FIG. 3
shows the voltage change in the case of transiting from the status selecting the memory cell MC
1
to the status selecting the memory cell MC
2
when data “1” is recorded to the memory cell MC
2
.
Before the address transits, the word line WL
1
is an active status, (e.g., high level), and the word line WL
2
is an inactive status, (e.g., low level). Because of this, MC
1
is selected, the bit line BLA becomes low level, and the bit line BLB becomes high level. In this case, the voltage level of the bit line BLA becomes the intermediate voltage between the power supply voltage VDD and the ground voltage VSS. The reason why the bit line becomes the intermediate voltage is that the load transistors Q
4
and Q
5
are always in ON state, and the electric charge from the power supply terminal VDD is supplied to the bit line BLA via the load transistors Q
4
and Q
5
.
As described above, by setting the low level voltages of the bit lines BLA and BLB to the intermediate voltage, the voltages of the bit lines BLA and BLB can quickly be raised to an initialized voltage during the address transition as described later. Additionally, the initialized voltage is the same voltage as the power voltage VDD.
On the other hand, when the address transits, the word line WL
1
becomes an inactive state, whereby the memory cell MC
1
becomes a non-selected state. Moreover, since the signal FI
1
reaches the low level during the address transition period, the equalizing transistor Q
1
is in ON state, and both of the bit lines try to reach the same voltage. At the same time, the precharge transistors Q
2
and Q
3
become ON state, and as a result, the bit lines BLA and BLB are charged to reach the same voltage level as the initialized voltage VDD via the precharge transistors Q
2
and Q
3
.
As described above, in the circuit of
FIG. 1
, by using the equalizing transistor Q
1
and precharge transistors Q
2
and Q
3
, while equalizing the bit lines BLA and BLB, and precharging to reach the level of the voltage VDD when the address transits, the bit line voltages are initialized.
Moreover, when the initialization processing of the bit lines BLA and BLB is started (time T
1
of FIG.
3
), the low level voltages of the bit lines BLA and BLB are set to the intermediate voltage between the power voltage VDD and the ground voltage VSS, and the voltages of the bit lines BLA and BLB can quickly be raised to the initialized voltage VDD.
Subsequently, the signal FI
1
showing in
FIG. 1
returns to the high level, the equalizing transistor Q
1
and precharge transistors Q
2
and Q
3
are placed in OFF state, and the initialization processing of the bit line voltages is finished. At the same time, the word line WL
2
becomes the active state by the address transition, and the memory cell MC
2
is selected. When data “1” is stored in the memory cell MC
2
, the voltage of the bit line BLB reaches the low level, and the voltage of the bit line BLA reaches the high level.
In this case, since the load transistors Q
4
and Q
5
are in ON state, the voltage of the bit line BLB reaches the intermediate level between the power voltage VDD and the ground voltage VSS.
However, the circuit of
FIG. 1
has a problem that the low level voltages of the bit lines BLA and BLB does not quickly lower until the desired voltages after the initialization processing of the bit lines BLA and BLB is finished.
More specifically, in the circuit of
FIG. 1
, at the same time when the initialization processing of the bit lines BLA and BLB is finished, the word line WL
2
becomes the active state. Therefore, the data of the memory cell MC
2
is outputted to the bit line BLB, and the bit line BLB reaches the low level. However, since the load transistors Q
4
and Q
5
are always in ON state, the bit line BIB is always supplied with the electric charge via the load transistors Q
4
and Q
5
. Therefore, the voltage amplitude of the bit line BLB does not increase soon, and an access time delay occurs.
SUMMARY OF THE INVENTION
The present invention has been developed in consideration of the above-described respects, and an object thereof is to provide a semiconductor memory device which can increase the voltage amplitude of bit lines in a short time during change-over between selection and non-selection of memory cells.
To attain the above-described object, according to the present invention, there is provided a semiconductor

Affiliated with

Also associated with

Rating

Semiconductor memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2470219