Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
1999-12-27
2001-07-24
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S194000, C327S298000
Reexamination Certificate
active
06266283
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device, and more particularly to a data input/output device for a semiconductor memory device provided with a delay circuit for synchronizing in timing between a clock signal and a data stroboscopic signals and data signals.
As the high speed performance of the computer system has been improved, the high speed performance of the semiconductor memory device depends upon the data transfer rate. There was proposed a double data rate for conducting two times data input/output operations in one clock in order to improve the data transfer rate.
FIG. 1
is a timing chart illustrative of waveforms of double data rate operations static random access memory. Data stroboscopic signals (DQS) and data signals (DQ) are outputted in synchronizing with rising edge of clock signal (CLK) and reversed phase clock signal (CLBK), so that two times of the data input and output operations are conducted in one clock. In order to realize the double data rate, there are used a clock synchronizing circuit with a feed-back system such as a phase-locked loop and a delay-locked loop, and a clock synchronizing circuit with a sequence control system such as a synchronous mirror delay as disclosed in Japanese laid-open patent publication No. 8-237091 and a clock supplying semiconductor circuit as disclosed in Japanese laid-open patent publication No. 9-152656.
FIG. 2
is a block diagram illustrative of a circuit configuration of a digital delay-locked loop circuit. The clock signal CLK and the reversed phase clock signal CLKB are inputted into two input terminals. First and second output enable signal generator systems
500
and
510
are provided, each of which is connected to the two input terminals individually. The first and second output enable signal generator systems
500
and
510
generate output enable signals
1
and
2
respectively on the basis of the inputs of the clock signal CLK and the reversed phase clock signal CLKB. An output circuit
520
is provided which is connected to the individual output terminals of the first and second output enable signal generator systems
500
and
510
. The output circuit
520
receives the output enable signals
1
and
2
from the first and second output enable signal generator systems
500
and
510
so that the output circuit
520
generates a data signal DQ or a data stroboscopic signal SQS in accordance with the output enable signals
1
and
2
and internal data. An end circuit
530
is provided which is connected to the output circuit
520
for receiving the data signal DO or the data stroboscopic signal SQS from the output circuit
520
so that the end circuit
530
generates a signal necessary for access measurement on the basis of the data signal DQ or the data stroboscopic signal SQS. Each of the first and second output enable signal generator systems
500
and
510
has an input first stage circuit
501
which is connected to the two input terminals for receiving the clock signal CLK and the reversed phase clock s:. Each of the first and second output enable signal generator systems
500
and
510
also has a delay circuit alignment
502
connected to the input first stage circuit
501
for receiving an output signal from the input first stage circuit
501
for delaying the output signal. Each of the first and second output enable signal generator systems
500
and
510
also has a buffering circuit
506
which is connected to the delay circuit alignment
502
for receiving an output signal from the delay circuit alignment
502
. Each of the first and second output enable signal generator systems
500
and
510
also has a delay device
505
which is connected to the delay circuit alignment
502
for delaying the output signal from the delay circuit alignment
502
in consideration of the delay times of the input first stage circuit
501
, the buffering circuit
506
, the output circuit
520
, and the end circuit
530
. The delay device
505
delays the output signal
4
from the delay circuit alignment
502
to generate a delayed output signal
5
. Each of the first and second output enable signal generator systems
500
and
510
also has a phase comparator
503
which has two inputs connected to the output of the input first stage circuit
501
for receiving the output signal
3
from the input first stage circuit
501
and also receiving the output signal
5
from the delay device
505
, so that the phase comparator
503
compares phases between the output signals
3
and
5
. Each of the first and second output enable signal generator systems
500
and
510
also has a control circuit
504
which is connected to the phase comparator
503
for receiving an output from the phase comparator
503
to generate a control signal on the basis of the output signal from the phase comparator
503
. The control circuit
504
is also connected to the delay circuit alignment
502
to send the control signal to the delay circuit alignment
502
for controlling the delay of the delay circuit alignment
502
. The first and second output enable signal generator systems
500
and
510
are different only in operations in reversed phases to each other.
FIG. 3
is a timing chart illustrative of waveforms in operations of the delay-locked loop circuit of FIG.
2
. “t
0
” is a delay time defined from a cross point of a rising or falling edge of the clock signal (CLK) and the reversed phase clock signal (CLKB) to a rising edge of the output signal
3
from the input first stage circuit
501
. “t
1
” is a delay time defined from a rising edge of the output enable signals
1
and
2
of the output circuit
520
to an access measurement point of the end circuit
530
. “t
2
” is a delay time defined from the rising edge of the reference signal
4
to the rising edge of the output enable signal. “t
5
” is a delay time of the delay device
505
.
The delay time “t
5
” of the delay device
505
is given by the following equation.
t
5
=(t
0
+t
1
+t
2
) (1)
Skew tAC and tDQSCK of he clock signal CLK or the reversed phase clock signal CLKB and the data signal DQ and the data stroboscopic signal DQS are adjusted to the following regulation. The delay device
505
delays in a total amount of individual delay times of the input first stage circuit
501
, the output circuit
520
, the end circuit
530
and the buffering circuit
506
, so that a timing synchronizing between the output signals
3
and
5
is made by the phase comparator
503
and the control circuit
504
.
FIG. 4
is a block diagram illustrative of a clock supplying semiconductor circuit.
FIG. 5
is a timing chart illustrative of waveforms of a clock supplying semiconductor circuit of
FIG. 4
An output enable signal generating system
700
has an input first state circuit
501
, control circuits
710
and
780
, delay circuit alignments
760
and
790
and pulse generator circuits
770
and
800
. The output enable signal generating system
700
generates an output enable signal
1
which is to be inputted into the input circuit
520
. An output enable signal generating system
810
has the same circuit configuration as the output enable signal generating system
700
. The output enable signal generating system
810
generates an output enable signal
2
which is to be inputted into the input circuit
520
. The end circuit
530
is connected to the output terminal o the output circuit
520
. The delay circuit alignment
760
has four delay circuits
720
,
730
,
740
and
750
. There are provided two flip-flop circuits
702
and
711
, two AND-gates
712
and
773
. The pulse generator circuit
770
has a delay circuit
771
. There are provided three inverters
701
,
703
and
705
. A delay device
704
is further provided for timing synchronization of the clock supply semiconductor circuit.
A delay time “t
6
” of the delay device
704
is defined to be represented by the following equation.
t
6
=(t
0
+t
1
+t
2
+t
3
×2) (2)
Skew tAC and tDQSCK of he clock signal
Le Vu A.
NEC Corporation
Young & Thompson
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