Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1986-11-12

1988-09-27

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Precharge

365233, G11C 700

Patent

active

047746912

ABSTRACT:
An active pull-up circuit driving system 2 starts, sequentially with a prescribed time lag, active pull-up operation of the bit lines in memory cell array blocks MA1 to MA4, so that a peak value of electric current consumed at the time of starting active pull-up operation can be reduced. A precharge circuit driving system 3 starts, sequentially with a prescribed time lag, precharge operation of the bit lines in the memory cell array blocks MA1 to MA4, so that a peak value of electric current consumed at the time of starting bit line precharging operation can be reduced.

REFERENCES:
patent: 4044339 (1977-08-01), Berg
patent: 4636987 (1987-01-01), Norwood et al.
"A 60 ns 256K.times.1 Bit DRAM Using LD.sup.3 Technology and Double-Level Metal Interconnection", R. A. Kertis et al, IEEE Journal of Solid-State Circuits, vol. SC-19, No. 5, Oct. 1984, pp. 585-589.
"A 1-Mbit CMOS DRAM with Fast Page Mode and Static Column Mode" IEEE JNL. of Solid State Circuits, vol. SC-20, No. 5, Oct. 1985.

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