Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1995-11-03

1998-01-06

Popek, Joseph A.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365203, 365205, G11C 700

Patent

active

057062293

ABSTRACT:
A semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of pairs of bit lines to each of which the plurality of memory cells arranged in the column direction are connected, a plurality of latch type amplifiers each of which is provided between the bit lines of a corresponding one of the bit line pairs to amplify a potential difference between the bit lines, a plurality of activation circuits for respectively activating the plurality of latch type amplifiers, a data bus acting as passages of input data, a plurality of latch type storage circuits each of which is provided on a corresponding one of the columns and connected to the data bus, for temporarily storing the input data, a plurality of transfer gates for transferring the input data from the latch type storage circuits to the latch type amplifiers, and a transfer control circuit for controlling the transfer gates to simultaneously transfer the input data from the latch type storage circuits to the latch type amplifiers for each of the rows, wherein the memory cell array is divided into a plurality of sub-arrays including a preset number of columns and the activation circuits are provided for the respective sub-arrays.

REFERENCES:
patent: 4855959 (1989-08-01), Kobayashi
patent: 4972376 (1990-11-01), Torimaru et al.
patent: 5053998 (1991-10-01), Kannan et al.
patent: 5111386 (1992-05-01), Fujishima et al.
patent: 5138578 (1992-08-01), Fujii
patent: 5241503 (1993-08-01), Cheng

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