Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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365230, 365238, G11C 1140

Patent

active

043542565

ABSTRACT:
A semiconductor memory device, comprising N memory cell arrays each of which includes a plurality of memory cells, is arranged to enable the use of said semiconductor memory device in the form of both one-bit-per-word N-bits-per-word. Two separate sets of output gates are provided, together with an additional input line for selecting between the two sets of gates. One set of gates is connected to provide one-bit output, and the other set of gates is connected to provide N-bit output.

REFERENCES:
patent: 3763480 (1973-10-01), Weimer
patent: 3857046 (1974-12-01), Varadibrairwood et al.
patent: 3930239 (1975-12-01), Salters et al.
IEEE Journal of Solid-State Circuits vol. SC11, No. 5, Oct. 1976, "Two 4K Static 5-V Rams" pp. 602-609.

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