Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1999-02-05

2000-10-10

Nguyen, Tan T.

Static information storage and retrieval

Read/write circuit

Precharge

365204, G11C 700

Patent

active

061308463

ABSTRACT:
An approach to rapidly pre-charging bit lines (104a and 104b) after a write operation to a memory cell (128) is disclosed. Following a write operation, a Y-select signal (Yj) and its inverse (/Yj) are maintained in an active state for a given period of time, keeping the transistors within a column selecting circuit (102) turned on. Pre-charging circuits (106 and 108) are also turned on. Consequently, the bit lines (104a and 104b) are pre-charged by the bit line pre-charging circuit (106), and by the pre-charging circuit (108) by way of a read bus (124) and the column selecting circuit (102). Furthermore, a write amplifier (112) is also activated, resulting in the bit lines (104a and 104b) being further pre-charged by way of a write bus (126) and the column selecting circuit (102).

REFERENCES:
patent: 4996671 (1991-02-01), Suzuki et al.
patent: 5777935 (1998-07-01), Pantelakis et al.
patent: 5946264 (1999-08-01), McClure

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