Semiconductor memory device

Details Semiconductor memory device Semiconductor memory device

1984-01-04

1986-03-11

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Having particular data buffer or latch

365130, 365193, 365194, 365235, G11C 1140

Patent

active

045758255

ABSTRACT:
Disclosed is a semiconductor memory device which is one of three types of semiconductor memory devices, one operable only in page mode, one operable only in nibble and one operable selectively in page mode or nibble mode, being obtained from a partially unconnected semiconductor memory device through alternations in a portions in wiring. The semiconductor memory device includes first and second internal column address strobe signal generator. The second internal column address strobe signal generator has at the first stage thereof a NAND circuit one of inputs to which determines the type of the semiconductor memory device depending on which of three kinds of signals is selected as the input. Selection of such an input is effected by an aluminum wiring process using a mask. Such selection of the input causes variation in the input response characteristics of the output of the second internal column address strobe signal generator, thus providing a desired response appropriate for the selected mode or modes.

REFERENCES:
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4344156 (1982-08-01), Eaton, Jr. et al.
patent: 4491910 (1985-01-01), Caudel et al.
patent: 4510602 (1985-04-01), Engdahl et al.
"A 100ns 64K Dynamic RAM Using Redundancy Techniques," by S. Sheffield et al., Feb. 18, 1981 IEEE, International Solid-State Circuits Conf. Proceedings, pp. 84-85.

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