Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Multiplexing

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Details

36518905, 3652385, G11C 800

Patent

active

057176370

ABSTRACT:
The semiconductor memory device includes two sense amplifiers provided corresponding to data lines and a switching circuit for selectively connecting any two among the data lines to the two sense amplifiers, respectively. The data stored in one of the memory cells is amplified to be transmitted to an output buffer via the data line connected to one of the sense amplifiers. In parallel with this operation, the data stored in a next memory cell is amplified via the data line connected to another sense amplifier so as to be made valid. In this manner, after the data stored in one of the memory cell is transmitted to the output buffer, the data stored in the next memory cell is subsequently transmitted to the output buffer.

REFERENCES:
patent: 4887242 (1989-12-01), Hashimoto
patent: 5257235 (1993-10-01), Miyamoto

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