Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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365208, G11C 700

Patent

active

057577072

ABSTRACT:
A semiconductor memory device of this invention includes a memory cell array, a pair of input/output lines, a pair of column data lines for connecting the memory cell array to the pair of input/output lines, and resistors for capacitively dividing the pair of column data lines into a pair of bit lines and a pair of amplification lines. A sense amplifier for amplifying the potential difference between the pair of column data lines includes a restore circuit connected to the pair of bit lines and a sense circuit connected to the pair of amplification lines. Equalizers for equalizing the potential difference between the pair of column data lines are respectively arranged for the pair of bit lines and the pair of amplification lines.

REFERENCES:
patent: 5068831 (1991-11-01), Hoshi
patent: 5243574 (1993-09-01), Ikeda
patent: 5313434 (1994-05-01), Abe
patent: 5331233 (1994-07-01), Urakawa
patent: 5463584 (1995-10-01), Hoshino

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