Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1991-09-10
1993-06-08
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365210, G11C 1300
Patent
active
052185729
ABSTRACT:
A semiconductor memory device comprises a plurality of normal memory cell arrays having a first and a second data state, a plurality of redundant memory cell arrays having a first and a second data state for substituting for the normal memory cell arrays, a plurality of input/output lines, a plurality of complementary input/output lines, a plurality of first control signals for substituting a redundant memory cell array having the first data state for a defective normal memory cell array having the first data state, and a plurality of second control signals for substituting a redundant memory cell array having the second data state for a defective normal memory cell array having the second data state. In the device, a control circuit for transmitting the complementary input/output data to the plurality of input/output lines, and the input/output data to the plurality of complementary input/output data lines according to the circumstances is provided. Accordingly, the yield of semiconductor memory devices can be improved by increasing the potential number of redundant memory cells which can be substituted for defective normal memory cells.
REFERENCES:
patent: 5043943 (1991-08-01), Crisp et al.
Huh Boo-yung
Lee Jeon-Hyoung
Fears Terrell W.
Samsung Electronics Co,. Ltd.
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