Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Precharge

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Details

365205, 365207, 365208, 365190, 365227, G11C 11419

Patent

active

061445991

ABSTRACT:
In a DRAM semiconductor device comprising a bit line equalizer for setting a potential on paired bit lines to a potential on a precharge power source line, a sense amplifier circuit amplifying a potential difference across the paired bit lines and detecting data, sense amplifier drive lines, for applying a sense amplifier drive signal for driving the sense amplifier circuit to the sense amplifier circuit, and a sense amplifier/drive line equalizer, a current limiter element is so provided that, between a precharge power source line and the sense amplifier drive line, it is connected in series with the current path of the equalizer. By so providing the current limiter element, it is possible to, even if there occurs any cross-fail between the bit line and the word line, reduce a short-circuiting current at a precharging time or prevent generation of the short-circuiting current.

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