Semiconductor memory device

Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch

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Details

365230, 357 23, G11C 1300

Patent

active

043843476

ABSTRACT:
A semiconductor memory device comprising a plurality of memory blocks each including a sense amplifier array and a pair of memory cell groups disposed on both sides of the sense amplifier array, a row decoder for selecting a row line in the plurality of memory blocks, pairs of bus lines, each pair corresponding to one of the sense amplifier arrays and, a column decoder. The column decoder is provided commonly to the plurality of memory blocks and selectively connects a pair of input/output terminals of a sense amplifier of the sense amplifier array in each of the memory blocks to a corresponding one of the pairs of bus lines.

REFERENCES:
patent: 4012757 (1977-03-01), Koo
Electronics, "What to Expect Next: A Special Report" by John G. Posa, May 22, 1980, vol. 53, No. 12, pp. 119-122.

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